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1.发明公开Method and apparatus for generating a zero bit status flag in a microprocessor 失效方法和装置用于在微处理器制造Nullbitzustandsflagge
公开(公告)号：EP0730219A3
公开(公告)日：1998-07-29
申请号：EP96103210
申请日：1996-03-01
发明人： SIMONE MICHAEL A
CPC分类号： G06F9/30043 , G06F9/30094
摘要： A method and apparatus for generating a zero flag (z-flag) status signal in a microprocessor includes a z-flag signal generator that generates a z-flag signal from unaligned data simultaneous to the load alignment of such data. The z-flag generator first performs a zero detect on each byte of data retrieved from memory. The zero detect results are next decoded according to bit selection signals generated from a data format code which corresponds to the specific format of the retrieved data.
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公开(公告)号：EP0834125A1
公开(公告)日：1998-04-08
申请号：EP96917217.0
申请日：1996-06-05
CPC分类号： G06F11/1008 , H03M13/15
摘要： A method and apparatus are disclosed for detecting and correcting errors in the data stored within the entries of a memory table. Each time data is entered into the memory table, an error code generator generates a corresponding error code using the data. This error code is stored in the memory table along with the corresponding data. When an entry in the memory table is read out, an error detector receives the outputted data and its corresponding error code and processes the data and the error code to determine whether the outputted data contains any errors. If the outputted data contains any errors, the outputted data and error code are sent to an error correction unit. In response, the correction unit attempts to find single and double bit errors in the data by way of a compact and efficient computer program. If either a single or double bit error is found, the error correction unit corrects the error or errors to derive a set of corrected data. This corrected data is then written back to the proper entry within the memory table to correct the error or errors in the data. Data errors within the memory table are thus detected and corrected.
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公开(公告)号：EP0829048A2
公开(公告)日：1998-03-18
申请号：EP96916908.0
申请日：1996-05-31
发明人： SAVKAR, Sunil , SHEN, Gene , SAJJADIAN, Farnad , SHEBANOW, Mike
CPC分类号： G06F11/3648
摘要： A system and method providing a programmable hardware device within a CPU. The programmable hardware device permits a plurality of instructions to be trapped before they are executed. The instructions that are to be trapped are programmable to provide flexibility during CPU debugging and to ensure that a variety of application programs can be properly executed by the CPU. The system must also provide a means for permitting a trapped instruction to be emulated and/or to be executed serially.
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公开(公告)号：EP0813713A1
公开(公告)日：1997-12-29
申请号：EP96909505
申请日：1996-02-29
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1009
摘要： A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (101) (TLB) and, possibly, a translation table (116) held in memory (106) and implemented as a B-tree data structure. The TLB is initially searched for a translation for a specified input address (104). If exactly one valid entry of the TLB stores a translation for the specified input address then the output address (129) corresponding to the specified input address is determined from the contents of that entry. Otherwise, the translation table is searched for a translation for the specified input address. If two or more valid entries of the TLB store a translation for the specified input address then these entries are invalidated. A translation for the specified input address and possibly one or more translations for other input addresses that are stored together with the translation for the specified input address are taken from the translation table and inserted into the TLB.
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公开(公告)号：EP0730224A3
公开(公告)日：1997-05-28
申请号：EP96103208.3
申请日：1996-03-01
发明人： Shebanow, Michael C. , Gmuender, John , Simone, Michael A. , Szeto, John R.F.S , Maruyama, Takumi , Tovey, DeForest W.
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the available registers for executing the instructions ready for execution. An oldest-instruction selector selects the M oldest instructions responsive to the precedence matrix and the eligible queue entry signals. The instruction queue provides the M selected instructions to execution units for execution. Upon completing the instructions, the execution units provide register availability signals to the dependency checker to release the registers used for the instructions.
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公开(公告)号：EP0730224A2
公开(公告)日：1996-09-04
申请号：EP96103208.3
申请日：1996-03-01
发明人： Shebanow, Michael C. , Gmuender, John , Simone, Michael A. , Szeto, John R.F.S , Maruyama, Takumi , Tovey, DeForest W.
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the available registers for executing the instructions ready for execution.
An oldest-instruction selector selects the M oldest instructions responsive to the precedence matrix and the eligible queue entry signals. The instruction queue provides the M selected instructions to execution units for execution. Upon completing the instructions, the execution units provide register availability signals to the dependency checker to release the registers used for the instructions.摘要翻译： 指令选择器每个时钟周期接收M个指令，并将N个指令存储在指令队列存储器中。 指令队列产生指示N个指令的年龄的优先矩阵。 依赖检查器确定用于执行准备执行的指令的可用寄存器。 最古老的指令选择器根据优先矩阵和符合条件的队列输入信号来选择M个最旧的指令。 指令队列将M个选择的指令提供给执行单元以供执行。 完成指令后，执行单元向依赖检查器提供寄存器可用性信号，以释放用于指令的寄存器。
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7.发明公开Method and apparatus for rapid execution of control transfer instructions 失效Verfahren und Vorrichtung zur schnellenAusführungvon Verzweigungsbefehlen
公开(公告)号：EP0730220A2
公开(公告)日：1996-09-04
申请号：EP96103171.3
申请日：1996-03-01
发明人： Savkar, Sunil W.
IPC分类号： G06F9/32
摘要： A method and apparatus accepts a relative control transfer instruction and generates a compact absolute control transfer instruction which may have a number of bits one greater than the relative control transfer instruction and including flags to rapidly construct the target address of the relative control transfer instruction. The compact absolute control transfer instruction is generated by sign extending the displacement of the relative control transfer instructions and adding it to a set of least significant bits from the control transfer instruction address, and optionally coupling some or all of the bits from the result with the original opcode or a different opcode. The target address of the relative control transfer instruction is determined by using, incrementing or decrementing, depending on the state of the flags, a group of the most significant bits from the relative control transfer instruction address and appending the result with the least significant bits from the result of the addition described above.
摘要翻译： 一种方法和装置接受相对控制传输指令，并产生紧凑的绝对控制传送指令，该指令可以具有比相对控制传送指令大一位的位数，并且包括用于快速构建相对控制传送指令的目标地址的标志。 紧凑的绝对控制传送指令是通过扩展相对控制传送指令的位移并将其从控制传送指令地址添加到一组最低有效位的符号来生成的，并且可选地将结果中的一些或全部位与 原始操作码或不同的操作码。 相对控制传送指令的目标地址是根据标志的状态通过使用，递增或递减来确定的，来自相对控制传送指令地址的最高有效位组，并将结果与最低有效位相加 上述添加的结果。
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8.发明公开Method and apparatus for efficiently writing results to renamed registers 失效一种用于有效地结果写入到寄存器具有改变名称的方法和装置
公开(公告)号：EP0727736A2
公开(公告)日：1996-08-21
申请号：EP96101840.5
申请日：1996-02-08
CPC分类号： G06F9/3836 , G06F9/384
摘要： A method and apparatus stores result data from an execution unit into a physical destination register in a register renaming superscaler microprocessor. The destination register number is associated with the result data and sent to a decoder which decodes the destination register number and enables the destination register corresponding to the destination register number to accept the result data broadcast to the physical destination registers.
摘要翻译： 的方法和装置存储产生于在执行单元数据转换成在寄存器重命名的超标量微处理器的物理目的地寄存器。 目的地寄存器编号与结果数据相关联，并且发送到解码器，其解码目的地寄存器编号，并且使目的寄存器对应于目的地寄存器编号接受广播到物理目的地寄存器中的结果的数据。
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9.发明公开Method and apparatus for prioritizing and handling errors in a computer system 失效在计算机系统中优先和处理错误的方法和装置
公开(公告)号：EP0730230A3
公开(公告)日：1999-12-22
申请号：EP96103124.2
申请日：1996-03-01
CPC分类号： G06F11/073 , G06F11/0793
摘要： A computer system (10) includes a central processing unit (12) and a memory management unit (18) having a plurality of functional units, such as a memory interface unit, a remote interface unit (60), a cache interface unit (70), and a translation unit (50). Each functional unit has a low priority error queue for storing error information for errors having a low priority. Some functional units also have a high priority error queue for storing error information for errors having a high priority error. Based on the status of the error queues, the memory management unit prioritizes and handles errors caused by hardware failures. For low priority errors, an interrupt request signal is sent to the central processing unit (122). For high priority errors, a RED ALERT signal is sent to the processing unit (112) to cause the processing unit to give immediate attention to the error. For high priority error queue overflows, a failure signal is generated (102) which causes the system to be halted and the contents of the system to be scanned out (104). Thus, errors are prioritized and handled accordingly.
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公开(公告)号：EP0730225A3
公开(公告)日：1999-12-08
申请号：EP96103209.1
申请日：1996-03-01
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： In a microprocessor, an apparatus is included for coordinating the use of physical registers in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts source and destination logical registers from the instruction. For the destination logical register, the apparatus assigns a physical address to correspond to the logical register. In so doing, the apparatus stores the former relationship between the logical register and another physical register. Storing this former relationship allows the apparatus to backstep to a particular instruction when an execution exception is encountered. Also, the apparatus checks the instruction to determine whether it is a speculative branch instruction. If so, then the apparatus creates a checkpoint by storing selected state information. This checkpoint provides a reference point to which the processor may later backup if it is determined that a speculated branch was incorrectly predicted. Overall, the apparatus coordinates the use of physical registers in the processor in such a way that: (1) logical/physical register relationships are easily changeable; and (2) backup and backstep procedures are accommodated.
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