A digital information receiver (100) having a single oscillator (118) providing a clock signal to the receiver circuitry. The receiver (100) contains, in addition to the oscillator (118), an input signal processor (102), a symbol time loop, a demodulator (106), a transport decoder (108), a transport timing loop, one or more applications decoders (102) and a presentation device (116). The input signal processor (102) digitizes an input signal and resamples the input signal using an interpolator (204) such that the input signal is optimally sampled. The resampling is controlled by a symbol timing loop. In a first embodiment, the transport timing loop controls the frequency of the oscillator (118) using transmitter timing information contained in the received signal. In the second embodiment, the oscillator (1202) is a free running oscillator and the transport timing loop controls a numerically controlled counter (1002) that, in turn, controls presentation timing of the information carried by the information in the input signal. After the input signal is decoded, an output interpolator (1204) generates continuous signals from somewhat bursty signals for utilization by the presentation device.