公开(公告)号：EP1279232A4

公开(公告)日：2003-08-06

申请号：EP01910765

申请日：2001-02-16

申请人： SARNOFF CORP

发明人： LYONS PAUL WALLACE ,  ACAMPORA ALFONSE ANTHONY ,  BELTZ JOHN PRICKETT ,  D ALESSANDRO VICTOR VINCENT ,  PECOTA CLIFFORD ARTHUR

IPC分类号： H04N7/52 ,  H04N21/242 ,  H04N21/43 ,  H03M7/00 ,  H04N7/24 ,  H04N7/58 ,  H04N7/62

CPC分类号： H04N21/4302 ,  H04N7/52 ,  H04N21/242 ,  H04N21/4305

摘要： A device and method for utilizing a single clock signal (300) to generate a digital data stream signal for transmission in a compressed domain transmission system. The device includes a plurality of packetized elementary stream encoders (100) electronically coupled to a transport stream encoder (200) electronically coupled to an output interface (600) to generate the digital stream signal. The method uses the single clock reference signal (300) to operate each of the packetized elementary stream encoders (100) to generate a plurality of packetized elementary signals, operate the transport stream encoder (200) to form a transport stream signal from the plurality of packetized elementary stream signals, operate the output interface (600) to output the digital stream signal in a predetermined manner.

摘要翻译： 一种利用单个时钟信号（300）产生数字数据流信号以在压缩域传输系统中传输的设备和方法。 该设备包括电子耦合到传输流编码器（200）的多个打包基本流编码器（100），传输流编码器（200）电耦合到输出接口（600）以生成数字流信号。 该方法使用单个时钟参考信号（300）来操作每个打包基本流编码器（100）以生成多个打包基本信号，操作传输流编码器（200）以形成来自多个 打包的基本流信号，操作输出接口（600）以预定方式输出数字流信号。

公开(公告)号：EP0815676A4

公开(公告)日：2000-07-05

申请号：EP96909641

申请日：1996-03-15

申请人： SARNOFF CORP

发明人： STROLLE CHRISTOPHER HUGH ,  JAFFE STEVEN TODD ,  LYONS PAUL WALLACE

IPC分类号： H04L27/38 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04N21/242 ,  H04N21/43 ,  H04N21/438 ,  H04L27/06 ,  H03K9/00 ,  H04L27/14 ,  H04L27/22 ,  H04N5/00 ,  H04N5/44 ,  H04N7/24 ,  H04N7/62

CPC分类号： H04L7/0029 ,  H04L7/0278 ,  H04N21/242 ,  H04N21/4302 ,  H04N21/4382 ,  H04N21/4384

摘要： A digital information receiver (100) having a single oscillator (118) providing a clock signal to the receiver circuitry. The receiver (100) contains, in addition to the oscillator (118), an input signal processor (102), a symbol time loop, a demodulator (106), a transport decoder (108), a transport timing loop, one or more applications decoders (102) and a presentation device (116). The input signal processor (102) digitizes an input signal and resamples the input signal using an interpolator (204) such that the input signal is optimally sampled. The resampling is controlled by a symbol timing loop. In a first embodiment, the transport timing loop controls the frequency of the oscillator (118) using transmitter timing information contained in the received signal. In the second embodiment, the oscillator (1202) is a free running oscillator and the transport timing loop controls a numerically controlled counter (1002) that, in turn, controls presentation timing of the information carried by the information in the input signal. After the input signal is decoded, an output interpolator (1204) generates continuous signals from somewhat bursty signals for utilization by the presentation device.