发明公开
EP0834921A2 Multi-layer circuit construction method and structures with customization features and components for use therein 失效
多层电路构造方法和具有用于其中的定制特征和组件的结构

  • 专利标题: Multi-layer circuit construction method and structures with customization features and components for use therein
  • 专利标题(中): 多层电路构造方法和具有用于其中的定制特征和组件的结构
  • 申请号: EP97203302.1
    申请日: 1992-12-30
  • 公开(公告)号: EP0834921A2
    公开(公告)日: 1998-04-08
  • 发明人: Distefano, Thomas H.Khandros, IgorGrube, Gary W.Ehrenberg, Scott G.
  • 申请人: TESSERA, INC.
  • 申请人地址: 103 Fairview Park Drive Elmsford, NY 10523 US
  • 专利权人: TESSERA, INC.
  • 当前专利权人: TESSERA, INC.
  • 当前专利权人地址: 103 Fairview Park Drive Elmsford, NY 10523 US
  • 代理机构: Andersson, Per Rune
  • 优先权: US815401 19911231; US816634 19911231
  • 主分类号: H01L23/538
  • IPC分类号: H01L23/538
Multi-layer circuit construction method and structures with customization features and components for use therein
摘要:
The invention relates to a method of making a multi-layer circuit assembly. Said method comprises the steps of providing a first circuit panel (544) having a dielectric body with oppositely directed top and bottom surfaces, contacts (538) on its top surface at locations of a first pattern, terminals (530) on its bottom surface, and through-conductors (527) electrically connected to said terminals and extending to the top surface of the panel, and a second circuit panel (562) having a dielectric body with a bottom surface and terminals (530) at locations of said first pattern on the bottom surface of such panel, said providing step including the step of customizing said first circuit panel by selectively treating the top surface of such panel so that less than all of the through conductors of such panel are connected to contacts of such panel; stacking said circuit panels in superposed, top-surface to bottom surface relation so that the top surface of said first circuit panel faces the bottom surface of said second circuit panel at a first interface and said first patterns on said facing surfaces are in registration with one another, with said contacts of said first panel being aligned with said terminals of said second panel at least some locations of said inregistration patterns; and non-selectively connecting all of said aligned contacts and terminals at said interface, whereby less than all of said through conductors of said customized panel are connected to terminals of said adjacent panel. The invention also relates to a multi-layer circuit assembly.
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