发明公开
EP0882295A1 PIPELINED SAMPLE AND HOLD CIRCUIT WITH CORRELATED DOUBLE SAMPLING
失效
与流水线结构双重相关信号SCAN采样保持电路
- 专利标题: PIPELINED SAMPLE AND HOLD CIRCUIT WITH CORRELATED DOUBLE SAMPLING
- 专利标题(中): 与流水线结构双重相关信号SCAN采样保持电路
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申请号: EP97949488.0申请日: 1997-11-19
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公开(公告)号: EP0882295A1公开(公告)日: 1998-12-09
- 发明人: MALLINSON, Martin , ALLEN, Max, J. , COLBETH, Richard, E.
- 申请人: VARIAN ASSOCIATES, INC.
- 申请人地址: 3050 Hansen Way Palo Alto, California 94304 US
- 专利权人: VARIAN ASSOCIATES, INC.
- 当前专利权人: VARIAN ASSOCIATES, INC.
- 当前专利权人地址: 3050 Hansen Way Palo Alto, California 94304 US
- 代理机构: Foster, Mark Charles
- 优先权: US19960758536 19961129
- 国际公布: WO1998024092 19980604
- 主分类号: G11C27
- IPC分类号: G11C27
摘要:
A signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture includes a time multiplexed integrating amplifier circuit in which the output circuit is a pipelined sample and hold circuit which provides time multiplexed input signal samples and the feedback integration capacitor is discharged between samples. At all times, one of the channels of the pipelined sample and hold circuit is providing one of the time multiplexed input signal samples while the other channel continues tracking the input signal. The feedback integration capacitor acts as a clamp to null out residual reset noise received as part of the input signal to be sampled. Hence, with the exception of that very brief period of time necessary for switching between the two pipelined sample and hold circuit channels, one of the two pipelined sample and hold circuit channels is always available for signal acquisition.
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