The invention relates to non-volatile memory structure integrated on a semiconductor substrate and including a plurality of memory cells (1) each comprising a floating gate transistor having an active area (9) and source/drain (16, 17) regions as well as a control gate coupled to the floating gate, the floating gate transistor being serially connected to a selection transistor. According to the invention a contact (7) is provided on the control gate over the active area (9). The contact is substantially aligned to the central portion of the active area but may even be realized over double-poly wings (18, 19) of the gate region located asymmetrically with respect to the active area.