公开(公告)号：EP4498284A1

公开(公告)日：2025-01-29

申请号：EP24154497.2

申请日：2024-01-29

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： PAU, Danilo Pietro ,  SINGH, Surinder Pal ,  AYMONE, Fabrizio Maria

IPC: G06N3/045 ,  G06N3/047 ,  G06N3/084 ,  G06N3/044

Abstract: The present disclosure relates to a method of training a neural network (Net1) using a circuit comprising a memory (104) and a processing device (102), the method comprising: performing a first forward inference pass through the neural network based on input features to generate first activations, and generating an error based on a target value, and storing said error to the memory (104); and performing, for each layer of the neural network (Net1): a modulated forward inference pass; before, during or after the modulated forward inference pass, a second forward inference pass based on said input features to regenerate one or more first activations; and updating one or more weights in the neural network (Net1) based on the modulated activations and said one or more regenerated first activations.

公开(公告)号：EP4390935A1

公开(公告)日：2024-06-26

申请号：EP23216192.7

申请日：2023-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： ZURLA, Riccardo ,  PASOTTI, Marco ,  CARISSIMI, Marcella ,  CABRINI, Alessandro

IPC: G11C13/00 ,  G11C11/54 ,  G11C7/10 ,  G06N3/063

CPC classification number: G06N3/063 ,  G11C7/1006 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/007120130101 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/004520130101 ,  G11C11/54 ,  G11C13/0028 ,  G06N3/065

Abstract: An in-memory computation device (10) receives an input signal (X) indicative of a plurality of input values (x1,...,xN) and provides an output signal (y1,...,yM). The in-memory computation device has: a word line activation unit (14) that receives the input signal and provides activation signals (21), each as a function of an input value; a memory array (12) and a digital detector (22). The memory array has a plurality of memory cells (20) coupled to a bit line (BLi) and each to a word line (WLj). The memory cells store each a computational weight (gij), receive each an activation signal (21), and are flown through each by a cell current (icell) that is a function of the activation signal and the computational weight. The bit line is flown through by a bit line current (IBL,i) that is a summation of the cell currents. The digital detector is coupled to the bit line, has an integration stage (33) and a counter stage (34) and performs successive iterations. In each iteration: the integration stage generates an integration signal indicative of a time integral of the bit line current, compares the integration signal with a threshold, and resets the integration signal in response to the integration signal reaching the threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.

公开(公告)号：EP4387212A1

公开(公告)日：2024-06-19

申请号：EP23213677.0

申请日：2023-12-01

Applicant: STMicroelectronics S.r.l.

Inventor： RIZZARDINI, Federico ,  BRACCO, Lorenzo

IPC: H04M1/72454 ,  G06F1/16 ,  G06F3/0346

CPC classification number: H04M1/72454 ,  G06F1/16 ,  G06F3/0346

Abstract: A recognition system (1) for recognition of a gesture of bringing an electronic device (2), of a mobile or wearable type, to a user's ear (3), designed to be integrated in the electronic device (2) and having: a movement sensor (4), configured to provide a movement signal (Acc) indicative of the movement of the electronic device (2); an electrostatic charge variation sensor (5), configured to provide a charge variation signal (SQ) associated with the movement; a processing module (16), operatively coupled to the movement sensor (4) and to the electrostatic charge variation sensor (5) and configured to perform a joint processing of the movement signal (Acc) and the charge variation signal (SQ) for the recognition of the gesture.

公开(公告)号：EP4375618A1

公开(公告)日：2024-05-29

申请号：EP23207357.7

申请日：2023-11-02

Applicant: STMicroelectronics S.r.l.

Inventor： RIZZARDINI, Federico ,  BRACCO, Lorenzo

IPC: G01C21/16

CPC classification number: G01C21/185

Abstract: A device includes a memory and processing circuitry coupled to the memory. The processing circuitry, in operation: estimates an angular rate of change and determines a rotational versor based on the rotational data; and estimates a gravity vector based on the angular rate of change and the rotational versor. The processing circuitry generates a dynamic gravity vector based on the estimated gravity vector, a correction factor and an estimated error in estimated gravity vector. The processing circuitry estimates a linear acceleration and determines an acceleration versor based on the acceleration data, and determines the correction factor based on the linear acceleration. The processing circuitry estimates the error in the estimated gravity vector based on the acceleration versor.

公开(公告)号：EP4373038A1

公开(公告)日：2024-05-22

申请号：EP23207659.6

申请日：2023-11-03

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： DONDINI, Mirko ,  TRECARICHI, Calogero Andrea ,  RENNIG, Fred

IPC: H04L12/40

CPC classification number: H04L12/40006 ,  H04L2012/4021520130101 ,  H04L2012/4027320130101

Abstract: A processing system (10a) is described. The processing system (10a) comprises a processing circuit (64), a volatile memory (60a) and a CAN communication controller circuit (50). The CAN communication controller circuit (50) comprises configuration and status registers (520). A transmission handler circuit (502) and a reception handler circuit (504) are configured to transmit and receive data via the CAN core circuit (500) by exchanging data with the volatile memory (60a) based on the configuration data stored to the configuration and status registers (520), and standard and/or extended filter elements stored to the volatile memory (60a).
Specifically, the processing system (10a) further comprises a hardware host circuit (62a) comprising a non-volatile memory (642) configured to store first configuration data (CD1) and second configuration data (CD2), wherein the first configuration data (CD1) comprise configuration data to be transferred to the configuration and status registers (520) of the CAN communication controller circuit (50) and the second configuration data (CD2) comprise at least one standard and/or extended filter element to be transferred to the volatile memory (60a). A control circuit (620, 628, 632) is configured to manage an initialization mode, a reception mode and a transmission mode. Specifically, during the initialization mode (648), the hardware host circuit (62a) stores the first configuration data (CD1) to the configuration and status registers (520) and the second configuration data (CD2) to the volatile memory (60a).

公开(公告)号：EP4365944A1

公开(公告)日：2024-05-08

申请号：EP23207394.0

申请日：2023-11-02

Applicant: STMicroelectronics S.r.l.

Inventor： SANNA, Auroroa ,  SOMMA, Cristina ,  HALICKI, Damian

IPC: H01L23/498 ,  H01L23/50

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838

Abstract: A semiconductor device comprises a semiconductor die mounted at a die area (14) of a package (10) such as a BGA package with an array of electrically conductive balls (12) providing electrical contact for the semiconductor die. A power channel (16) is provided to convey power supply current towards the semiconductor die (14). The power channel (16) comprises a stack of electrically conductive planes (12A) between a current inflow plane (L8) opposite the die area (14) and a current outflow plane (L3) towards the die area (14). A distribution of electrically conductive balls (12) is coupled to the current inflow plane (L8) of the power channel (16) so that the power channel (16) provides current conduction paths towards the die area (14) for electrically conductive balls (12) in that distribution. Adjacent electrically conductive planes (12A) in the stack of the power channel (16) are electrically coupled with electrically conductive vias (120) extending therebetween. The electrically conductive planes (12A) are stacked in a stepped arrangement (Step1, Step2, Step3, Step4) wherein the number of stacked planes (12A) increases in steps in the direction from the distal end (PE) to the proximal end of the power channel (16). The current conduction paths towards the die area (14) thus have resistance values that decrease from the distal end (PE) to the proximal end of the power channel (16).
A uniform distribution of power supply current over the length of the power channel (16) is thus facilitated.

公开(公告)号：EP4361560A1

公开(公告)日：2024-05-01

申请号：EP23202344.0

申请日：2023-10-09

Applicant: STMicroelectronics S.r.l.

Inventor： CARULLI, Paola ,  FALORNI, Luca Giuseppe ,  FEDELI, Patrick ,  GUERINONI, Luca

IPC: G01C19/5762 ,  G01C19/5747

CPC classification number: G01C19/5762 ,  G01C19/5747

Abstract: A microelectromechanical gyroscope (10) with detection along a vertical axis is provided with a detection structure (10) having a movable structure (12), suspended above a substrate (13) so as to perform, as a function of an angular velocity (Ωz) around the vertical axis a sense movement along a first horizontal axis (x). The movable structure has at least one drive mass (14) internally defining a window (16), elastically coupled to a rotor anchor (20'), at an anchoring region (A), through elastic anchoring elements (21); at least one bridge element (18), rigid and of a conductive material, cantilevered suspended and extending within the window along the first horizontal axis, elastically coupled to the drive mass; movable electrodes (23), carried integrally by the bridge element with extension along a second horizontal axis (y). The detection structure (10) also has stator electrodes (28, 29), arranged in the window and interdigitated with the movable electrodes, at a certain separation distance below the bridge element (18), which extends longitudinally above the same stator electrodes and the movable electrodes.

公开(公告)号：EP4354350A1

公开(公告)日：2024-04-17

申请号：EP23199602.6

申请日：2023-09-26

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： FOLLIOT, Laurent ,  LATTUADA, Marco ,  DEMAJ, Pierre

IPC: G06N3/063 ,  G06N3/10

CPC classification number: G06N3/063 ,  G06N3/09 ,  G06N3/10

Abstract: Selon un aspect, il est proposé un procédé de génération d'un code exécutable par un ordinateur pour mettre en oeuvre un réseau de neurones artificiels (INN) comportant une élaboration (25) du code exécutable (ONN) en choisissant pour chaque couche du réseau de neurones (INN) une solution d'implémentation parmi les solutions d'implémentation possibles de cette couche en fonction de la perte de performances en termes de temps d'exécution et/ou d'allocation de cette solution d'implémentation par rapport au seuil de temps d'exécution maximal et/ou du seuil d'allocation mémoire maximale.

公开(公告)号：EP4345464A1

公开(公告)日：2024-04-03

申请号：EP23196500.5

申请日：2023-09-11

Applicant: STMicroelectronics S.r.l.

Inventor： DE VITA, Placido ,  ABBISSO, Salvatore ,  TORRISI, Giovanni Luca ,  LEONE, Antonio Davide

IPC: G01R1/20 ,  G01R1/44 ,  G01R19/00

Abstract: Described herein is a method for sensing at a pre-driving stage (12) driving one or more Field Effect Transistor (MHx, MLx), in particular MOSFET, comprised in a power stage (13) driving a load (DC1...DC4), a current flowing in said Field Effect Transistor (MHx, MLx), in particular MOSFET, the Field Effect Transistor being arranged external with respect to a chip on which said pre-driving stage (12) is arranged,
said method comprising
measuring (120) a drain to source voltage (VDS_HSx, VDS_LSx), of said one or more Field Effect Transistor (MHX, MLx),
measuring (130) an operating temperature (T W ) of said one or more Field Effect Transistor (MHX, MLx),
measuring (140) a current (IHX, ILx) flowing in said one or more Field Effect Transistor (MHX, MLx) by
calculating (142) the respective on drain to source resistance at the operating temperature (RdsONx(T W )) as a function (RdsONx(T W )) of said measured operating temperature (T W ) and by obtaining (144) said current (IHX, ILx) as the ratio of the respective measured drain to source voltage (VDS_HSx, VDS_LSx) over said calculated drain to source resistance at the operating temperature (RdsONx(T W )).

公开(公告)号：EP4319039A9

公开(公告)日：2024-03-20

申请号：EP23186442.2

申请日：2023-07-19

Applicant: STMicroelectronics S.r.l.

Inventor： QUARTIROLI, Matteo ,  MECCHIA, Alessandro ,  PESENTI, Paolo

IPC: H04L7/00 ,  H04L7/033

Abstract: A synchronizing digital device includes a reference input (26a), receiving a reference clock signal (CKB) at a reference clock frequency (F CKB ); an output (17); a local oscillator (14), providing a local clock signal (CKJ) having a local clock frequency (F CKJ ); a digital signal source (15), based on the local clock signal (CKJ) and providing digital signals (SD); and a synchronization stage (18). The synchronization stage (18) is based on the local clock signal (CKJ) and includes: a resampler (22), arranged between the digital signal source (15) and the output (17) and configured to make available resampled digital signals (SDRS), obtained by taking samples of the digital signals (SD) with a resampling frequency (F RS ); and a sigma-delta modulator (20) configured to cause the generation of a resampling signal (CKF) modulated on average at the resampling frequency (F RS ) as a function of the reference clock signal (CKB) and to control the resampler (22) through the resampling signal (CKF) .