发明公开
EP1037280A3 Memory cell layout for reduced interaction between storage nodes and transistors
审中-公开
Speicherzellenanordnung zur reduzierten Interaktion zwischen Speicherknoten und Transistoren
- 专利标题： Memory cell layout for reduced interaction between storage nodes and transistors
- 专利标题（中）： Speicherzellenanordnung zur reduzierten Interaktion zwischen Speicherknoten und Transistoren
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申请号： EP00103617.7申请日： 2000-02-21
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公开(公告)号： EP1037280A3公开(公告)日： 2001-04-11
- 发明人: Park, Young-Jin , Radens, Carl J. , Kunkel, Gerhard
- 申请人： Infineon Technologies North America Corp. , INTERNATIONAL BUSINESS MACHINES CORPORATION
- 申请人地址： 1730 North First Street San Jose, CA 95112-6000 US
- 专利权人： Infineon Technologies North America Corp.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： Infineon Technologies North America Corp.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： 1730 North First Street San Jose, CA 95112-6000 US
- 代理机构： Patentanwälte Westphal, Mussgnug & Partner
- 优先权： US272215 19990318
- 主分类号： H01L27/108
- IPC分类号： H01L27/108
摘要：
A memory cell, in accordance with the invention, includes a trench formed in a substrate, and an active area formed in the substrate below a gate and extending to the trench. The active area includes diffusion regions for forming a transistor for accessing a storage node in the trench, the transistor being activated by the gate. The gate defines a first axis wherein a portion of the active area extends transversely therefrom, the portion of the active area extending to the trench. The trench has a side closest to the portion of the active area, the side of the trench being angularly disposed relative to the gate such that a distance between the gate and the side of the trench is greater than a minimum feature size.
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