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公开(公告)号：EP1073115A3
公开(公告)日：2004-08-04
申请号：EP00306332.8
申请日：2000-07-25
发明人： Gruening, Ulrike , Radens, Carl J. , Tobben, Dirk
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087
摘要： A process for manufacturing a deep trench capacitor in a trench (10). The capacitor comprises a collar (18) in an upper region of the trench and a buried plate (26) in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material (16) such as spin-on-glass. The process may comprise the steps of (a) forming a deep trench in a substrate; (b) filling the trench lower region with an underfill material; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.
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2.发明公开Crystal-axis-aligned vertical side wall DRAM and process for manufacture thereof 审中-公开经由垂直对齐于侧壁的晶轴和方法及其制造DRAM
公开(公告)号：EP1071129A2
公开(公告)日：2001-01-24
申请号：EP00306232.0
申请日：2000-07-21
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.
摘要翻译： 一种动态随机存取存储器（DRAM）单元，包括具有有源晶体管器件在沟槽的侧壁上部分地设置在深沟槽存储电容器。 侧壁对准于具有沿单个晶轴的结晶取向的第一结晶学平面。 制造寻求的DRAM单元的方法，包括：（a）形成在衬底的深沟槽，（b）中沿沟槽侧壁上形成具有单一晶体取向的小平面晶体区，以及（c）形成晶体管器件部分地设置 在侧壁上的小平面晶体区。 例如通过选择以促进沿着比沿第二家庭晶轴的晶轴的第一家庭更高的氧化速率氧化条件下的局部热氧化：所述小平面晶体区可以由氧化物轴环，颜色的生长来形成。
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公开(公告)号：EP1039534A3
公开(公告)日：2001-04-04
申请号：EP00103845.4
申请日：2000-02-24
发明人： Gruening, Ulrike , Halle, Scott , Radens, Carl J. , Welser, Jeffrey J. , Beintner, Jochen , Mandelman, Jack A. , Wittmann, Juergen
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10861
摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.
摘要翻译： 一种方法包括在半导体本体中形成沟槽电容器。 在电容器的上部形成凹部，在半导体本体中具有侧壁。 第一材料沉积在凹槽的侧壁和底部上方。 第二种材料沉积在第一种材料上。 在第二材料上提供掩模。 掩模具有：掩蔽区域，以覆盖所述凹部底部的一部分; 以及位于所述凹陷侧壁的一部分上的窗口和所述凹陷底部的另一部分以暴露第二材料的下部。 第二材料的暴露下面的部分的部分是选择性地去除，同时留下第一材料的基本上未蚀刻的暴露的下部。 选择性地去除半导体主体的第一材料和下部的暴露部分。 在半导体本体的去除部分中形成隔离区。 所述掩模设置在所述第二材料上方，具有覆盖所述凹陷侧壁的一部分和所述凹部底部的一部分的掩蔽区域，以及设置在所述凹部侧壁的相对部分上方的窗口和所述凹部底部的相对部分， 第二材料的部分。 在半导体本体的暴露的下部设置蚀刻，以在半导体本体中形成浅沟槽。 在浅沟槽中形成绝缘材料以形成浅沟槽隔离区域。 通过这种方法，允许更大的掩模未对准公差。
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4.发明公开Crystal-axis-aligned vertical side wall DRAM and process for manufacture thereof 审中-公开晶轴对齐的垂直侧壁DRAM及其制造方法
公开(公告)号：EP1071129A3
公开(公告)日：2001-06-13
申请号：EP00306232.0
申请日：2000-07-21
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.
摘要翻译： 一种包括深沟槽存储电容器的动态随机存取存储器（DRAM）单元，所述深沟槽存储电容器具有部分地设置在沟槽侧壁上的有源晶体管器件。 侧壁与具有沿着单晶轴的晶体取向的第一晶面对齐。 用于制造这种DRAM单元的工艺包括：（a）在衬底中形成深沟槽，（b）沿着具有单一晶体取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分布置的晶体管器件 在侧壁中的多面晶体区域上。 有刻面的晶体区域可以通过生长氧化物轴环来形成，例如通过局部热氧化在氧化条件下进行，所述氧化条件选择为沿着第一族晶体轴促进更高的氧化速率，而不是沿着第二族晶体轴。
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公开(公告)号：EP1039534A2
公开(公告)日：2000-09-27
申请号：EP00103845.4
申请日：2000-02-24
发明人： Gruening, Ulrike , Halle, Scott , Radens, Carl J. , Welser, Jeffrey J. , Beintner, Jochen , Mandelman, Jack A. , Wittmann, Juergen
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10861
摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.
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6.发明公开Memory cell layout for reduced interaction between storage nodes and transistors 审中-公开Speicherzellenanordnung zur reduzierten Interaktion zwischen Speicherknoten und Transistoren
公开(公告)号：EP1037280A3
公开(公告)日：2001-04-11
申请号：EP00103617.7
申请日：2000-02-21
IPC分类号： H01L27/108
CPC分类号： H01L27/10829 , H01L27/0207 , H01L27/10882 , Y10S257/906 , Y10S257/907 , Y10S257/908
摘要： A memory cell, in accordance with the invention, includes a trench formed in a substrate, and an active area formed in the substrate below a gate and extending to the trench. The active area includes diffusion regions for forming a transistor for accessing a storage node in the trench, the transistor being activated by the gate. The gate defines a first axis wherein a portion of the active area extends transversely therefrom, the portion of the active area extending to the trench. The trench has a side closest to the portion of the active area, the side of the trench being angularly disposed relative to the gate such that a distance between the gate and the side of the trench is greater than a minimum feature size.
摘要翻译： 根据本发明的存储单元包括形成在衬底中的沟槽和形成在栅极下方并延伸到沟槽的衬底中的有源区。 有源区域包括用于形成用于访问沟槽中的存储节点的晶体管的扩散区域，晶体管由栅极激活。 门限定第一轴，其中有源区的一部分从其横向延伸，有源区的部分延伸到沟槽。 沟槽具有最靠近有源区域的一部分的一侧，沟槽的侧面相对于栅极角度地设置，使得栅极和沟槽侧面之间的距离大于最小特征尺寸。
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公开(公告)号：EP1073115A2
公开(公告)日：2001-01-31
申请号：EP00306332.8
申请日：2000-07-25
发明人： Gruening, Ulrike , Radens, Carl J. , Tobben, Dirk
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087
摘要： A process for manufacturing a deep trench capacitor in a trench. The capacitor comprises a collar in an upper region of the trench and a buried plate in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material such as spin-on-glass. The process may comprise the steps of (a) forming a deep trench in a substrate; (b) filling the trench lower region with an underfill material; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.
摘要翻译： 一种在沟槽（10）中制造深沟槽电容器的工艺。 电容器包括在沟槽的上部区域中的环（18）和在沟槽的下部区域中的掩埋板（26）。 改进之处在于，在沟槽上部区域中形成套环之前，用诸如旋涂玻璃的非感光底部填充材料（16）填充沟槽下部区域。 该方法可以包括以下步骤：（a）在衬底中形成深沟槽; （b）用底部填充材料填充沟槽下部区域; （c）在所述沟槽上部区域中形成套环; （d）去除底层填料; 和（e）在沟槽下部区域形成掩埋板。
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8.发明公开Memory cell layout for reduced interaction between storage nodes and transistors 审中-公开为存储节点和晶体管之间相互影响减小存储器单元装置
公开(公告)号：EP1037280A2
公开(公告)日：2000-09-20
申请号：EP00103617.7
申请日：2000-02-21
IPC分类号： H01L27/108
CPC分类号： H01L27/10829 , H01L27/0207 , H01L27/10882 , Y10S257/906 , Y10S257/907 , Y10S257/908
摘要： A memory cell, in accordance with the invention, includes a trench formed in a substrate, and an active area formed in the substrate below a gate and extending to the trench. The active area includes diffusion regions for forming a transistor for accessing a storage node in the trench, the transistor being activated by the gate. The gate defines a first axis wherein a portion of the active area extends transversely therefrom, the portion of the active area extending to the trench. The trench has a side closest to the portion of the active area, the side of the trench being angularly disposed relative to the gate such that a distance between the gate and the side of the trench is greater than a minimum feature size.
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9.发明公开Trench capacitor DRAM cell with vertical transistor 审中-公开Grabenkondensator-DRAM-Zelle mit vertikalem晶体管
公开(公告)号：EP1077487A3
公开(公告)日：2005-01-19
申请号：EP00307018.2
申请日：2000-08-16
发明人： Furukawa, Toshiharu , Horak, David V. , Radens, Carl J. , Gruening, Ulrich , Mandelman, Jack A. , Rupp, Thomas S.
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall (222,223) formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region (208) coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region (210) formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region (212) extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator (214) formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor (216) filling the trench and having a top surface, and a wordline (218,232) having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译： 动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面和沟槽的衬底中，该衬底具有形成在衬底中的侧壁（222,223）。 使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。 信号传送装置包括耦合到信号存储节点并从沟槽的侧壁延伸到衬底中的第一扩散区域（208），形成在衬底中的邻近衬底顶表面的第二扩散区域（210） 邻近所述沟槽的侧壁，沿着所述沟槽的侧壁在所述第一扩散区域和所述第二扩散区域之间延伸的沟道区域（212），沿着所述沟槽的侧壁形成的栅极绝缘体（214），所述栅极绝缘体沿着所述第一扩散区域 到第二扩散区域，填充沟槽并具有顶表面的栅极导体（216）和与栅极导体的顶表面相邻的底部和与沟槽的侧壁对准的一侧的字线（218,232）。
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公开(公告)号：EP1077487A2
公开(公告)日：2001-02-21
申请号：EP00307018.2
申请日：2000-08-16
发明人： Furukawa, Toshiharu , Horak, David V. , Radens, Carl J. , Gruening, Ulrich , Mandelman, Jack A. , Rupp, Thomas S.
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
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