The invention relates to a circuit for reducing a variable input voltage (Uein), especially a pulsed input voltage, to a working voltage (Uz, Uarb) that is fed to an evaluation circuit (10), wherein the input voltage (Uein) may be reduced to obtain the working voltage (Uz, Uarb) according to a division factor (F) supplied by at least one voltage divider (R1, R3, T1, R4; R7, R8, R2), wherein the at least one voltage divider (R1, R3, T1, R4; R7, R8, R2) can be regulated in such a way that the division factor (F) may be augmented with increasing input voltage (Uein) and lowered with reducing input voltage (Uein).