A method of manufacturing integrated circuits based on providing a test column of memory cells in the devices. A test control processor (100) and a test board (101) for gang testing of integrated circuits (00, 01, 10, 11, 20, ...). Cells in the test column are selected by a portion of the addresses which identifies a row in the main array on the device. A test is executed to determine a characteristic of the device and the results of that test are mapped to the portion of the address which identifies a row in the array. This produces a characteristic code address for the device which indicates the test results of the test. Access to the test column on the device is enabled and a bit is written in response to the characteristic code address in a memory cell on the test column. During manufacture the test column is read in order to classify the device according to the characteristic. This allows for storing in a look up format significant amounts of data about the characteristics of the device without requiring large amounts of memory on the device, and substantially relieving the testing system of a requirement for memory resources.