A data storage circuit (30). The data storage circuit comprises a data input (12') for receiving a data voltage (D') and a node (17') for receiving an interim voltage in response to the data voltage. The data storage circuit also comprises an output enable circuit (32) for providing at least one conditional path coupled to the node and for coupling the interim voltage to the node. The output enable circuit comprises a transistor (32p) having a first threshold voltage and operable to provide a conductive path along the at least one conditional path. The data storage circuit also comprises a data output (19') for providing an output voltage in response to the interim voltage at the node and a data retention circuit coupled between the node and the data output. The data retention circuit (18' and 20') comprises at least one transistor having a second threshold voltage higher in magnitude than the first threshold voltage.