公开(公告)号：EP1122547A2

公开(公告)日：2001-08-08

申请号：EP01200354.7

申请日：2001-01-31

申请人： Texas Instruments Incorporated

发明人： Heraçu, Keerthinarayan P. ,  Bosshart, Patrick W.

IPC分类号： G01R31/3183

CPC分类号： G01R31/3183

摘要： A method for generating charge sharing test vectors for a circuit is provided that includes providing an automatic test pattern generator operable to generate a first test vector (120) and a second test vector (122). The method further includes providing a test model (98) including a logic cell of a circuit and an auxiliary test circuit (100) where the auxiliary test circuit (100) includes a discharge AND gate (102) and a charge sharing AND gate (104). The method next provides for selecting an output of the discharge AND gate (104) as a target for a falling transition fault test vector generation by the automatic test pattern generator (124). The method next provides for generating a first test vector (120) for the test model (98) using the automatic test pattern generator (124) where the first test vector (120) provides an input pattern to discharge nodes of the logic cell. In addition, the discharge AND gate (102) evaluates to a logic level 1 for the first test vector (120). The method next provides for generating a second test vector (122) for the test model (98) using the automatic test pattern generator (124) where the second test vector (122) provides an input pattern to evoke the worst charge sharing behavior for the logic cell. In addition, the charge sharing AND gate (104) evaluates to a logic level 1 for the second test vector (122).

摘要翻译： 提供了一种用于产生用于电路的电荷共享测试向量的方法，其包括提供可操作以产生第一测试向量（120）和第二测试向量（122）的自动测试模式发生器。 该方法还包括提供包括电路的逻辑单元和辅助测试电路（100）的测试模型（98），其中辅助测试电路（100）包括放电与门（102）和电荷共享与门（104） ）。 该方法接下来提供用于选择放电与门（104）的输出作为由自动测试图案发生器（124）产生的下降转变故障测试向量的目标。 该方法接下来提供用于使用自动测试图案生成器（124）生成用于测试模型（98）的第一测试向量（120），其中第一测试向量（120）提供输入模式以排放逻辑单元的节点。 此外，放电与门（102）对于第一测试矢量（120）评估为逻辑电平1。 该方法接下来提供用于使用自动测试图案生成器（124）生成用于测试模型（98）的第二测试向量（122），其中第二测试向量（122）提供输入模式以唤起最差的电荷共享行为 逻辑单元。 此外，电荷共享与门（104）评估为第二测试矢量（122）的逻辑电平1。

公开(公告)号：EP1093128A2

公开(公告)日：2001-04-18

申请号：EP00303330.5

申请日：2000-04-19

申请人： Texas Instruments Incorporated

发明人： Bosshart, Patrick W.

IPC分类号： G11C7/10

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  H03K3/356156

摘要： A data storage circuit (30). The data storage circuit comprises a data input (12') for receiving a data voltage (D') and a node (17') for receiving an interim voltage in response to the data voltage. The data storage circuit also comprises an output enable circuit (32) for providing at least one conditional path coupled to the node and for coupling the interim voltage to the node. The output enable circuit comprises a transistor (32p) having a first threshold voltage and operable to provide a conductive path along the at least one conditional path. The data storage circuit also comprises a data output (19') for providing an output voltage in response to the interim voltage at the node and a data retention circuit coupled between the node and the data output. The data retention circuit (18' and 20') comprises at least one transistor having a second threshold voltage higher in magnitude than the first threshold voltage.

摘要翻译： 数据存储电路（30）。 数据存储电路包括用于接收数据电压（D'）的数据输入端（12'）和用于响应于数据电压来接收临时电压的节点（17'）。 数据存储电路还包括输出使能电路（32），用于提供至少一个耦合到节点的条件路径并用于将该临时电压耦合到节点。 输出使能电路包括具有第一阈值电压并且可操作以提供沿着至少一个条件路径的导电路径的晶体管（32p）。 数据存储电路还包括用于响应于节点处的中间电压提供输出电压的数据输出（19'）以及耦合在节点和数据输出之间的数据保持电路。 数据保持电路（18'和20'）包括具有第二阈值电压的至少一个晶体管，所述第二阈值电压的量值大于第一阈值电压。

公开(公告)号：EP0820147A3

公开(公告)日：1999-07-21

申请号：EP97305362.2

申请日：1997-07-17

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W.

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： In a preferred logic circuit embodiment (10), there is a precharge node (14) coupled to be precharged to a precharge voltage (V DD ) during a precharge phase and operable to be discharged during an evaluate phase. The circuit also includes a conditional series discharge path (22, 24, and 16) connected to the precharge node and operable to couple the precharge node to a voltage different than the precharge voltage. The conditional series discharge path includes a low threshold voltage transistor (22 or 24) having a first threshold voltage, and a high threshold voltage transistor (16) having a second threshold voltage higher in magnitude than the first threshold voltage, wherein a voltage connected to a gate of the high threshold voltage transistor is disabling during the precharge phase.

公开(公告)号：EP0279953A2

公开(公告)日：1988-08-31

申请号：EP87119350.4

申请日：1987-12-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W.

IPC分类号： G06F9/26 ,  G06F9/28

CPC分类号： G06F9/28 ,  G06F9/26 ,  G06F9/3017 ,  G06F9/30189

摘要： A computer system uses microcode subroutines to execute complex macroinstruction. Each macroinstruction is used to index a table (18). Simple macroinstructions have a single microinstruction counterpart in the table (18), and such microinstruction is performed directly in order to execute that macroinstruction. The table entry corresponding to more complex macroinstructions is a jump microinstruction, with the target of the microcode jump being an appropriate subroutine in microcode memory (16).

摘要翻译： 计算机系统使用微代码子程序执行复杂的宏指令。 每个宏指令用于索引表（18）。 简单的宏指令在表（18）中具有单个微指令对应方式，并且这种微指令被直接执行以执行该宏指令。 对应于更复杂的宏指令的表条目是跳转微指令，微代码跳转的目标是微代码存储器（16）中的适当子程序。

公开(公告)号：EP0180369A2

公开(公告)日：1986-05-07

申请号：EP85307393.0

申请日：1985-10-15

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W.

IPC分类号： G06F12/08

CPC分类号： G06F12/126 ,  G06F12/0864 ,  G06F12/1045

摘要： A cache memory addressable by both physical and virtual addresses includes a cache data memory (64) and a tag memory (66). The tag memory (66) is comprised of a virtual tag memory (68) and a physical tag memory (70). The physical and virtual tag memories are both addressable by the least significant bits (LSB) of the address signal to output tag portions of addresses associated with data stored in the cache data memory (64). A switch (78) selects between the outputs from the memories (68) and (70) under control of an arbitration unit (88). The arbitration unit (88) distinguishes between virtual or physical addresses input thereto. A comparator (100) compares the selected tag portion with the tag portion of the received address to determine if a match exists. If a match exists, the output of the cache data memory is selected with a switch (84).

摘要翻译： 通过物理和虚拟地址可寻址的高速缓存存储器包括高速缓存数据存储器（64）和标签存储器（66）。 标签存储器（66）由虚拟标签存储器（68）和物理标签存储器（70）组成。 物理和虚拟标签存储器可以通过地址信号的最低有效位（LSB）来寻址，以输出与存储在高速缓存数据存储器（64）中的数据相关联的地址的标签部分。 在仲裁单元（88）的控制下，开关（78）在来自存储器（68）和（70）的输出之间进行选择。 仲裁单元（88）区分输入到其的虚拟或物理地址。 比较器（100）将所选标签部分与接收到的地址的标签部分进行比较，以确定是否存在匹配。 如果存在匹配，则用开关（84）选择高速缓存数据存储器的输出。

公开(公告)号：EP0954101B1

公开(公告)日：2006-11-02

申请号：EP99201372.2

申请日：1999-04-29

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Srivastava, Pranjal ,  Bosshart, Patrick W. ,  Ko, Uming

IPC分类号： H03K19/096 ,  H03K19/003

CPC分类号： H03K19/0963

公开(公告)号：EP0820147B1

公开(公告)日：2004-10-06

申请号：EP97305362.2

申请日：1997-07-17

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W.

IPC分类号： H03K19/096 ,  H03K19/00

CPC分类号： H03K19/0963

公开(公告)号：EP1424775A1

公开(公告)日：2004-06-02

申请号：EP03027571.3

申请日：2003-12-01

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bosshart, Patrick W.

IPC分类号： H03K19/003 ,  H03K19/096

CPC分类号： H03K19/00361 ,  H03K19/0963

摘要： A dynamic logic circuit (30). The dynamic logic circuit comprises a precharge node (30 PN ) to be precharged to a precharge voltage (V DD ) during a precharge phase and a conditional discharge path (30 L , 30 DT ) connected to the precharge node. The conditional discharge path is operable, during an evaluate phase, to conditionally couple the precharge node to a voltage different than the precharge voltage. The dynamic logic circuit also comprises an output (OUT 3 ) for providing a signal in response to a state at the precharge node. Lastly, the dynamic logic circuit comprises voltage maintaining circuitry (30 KT1 , 30 KT2 ), coupled to the output, for coupling the precharge voltage to the precharge node during a portion of an instance of the evaluate phase when the conditional discharge path is not enabled during the instance of the evaluate phase.

摘要翻译： 动态逻辑电路（30）。 动态逻辑电路包括：（30 PN）到在预充电阶段和连接到所述预充电节点的有条件放电通路（30L，30 DT）被预充电到预充电电压（VDD）的预充电节点。 条件放电路径可操作，期间有条件地将预充电节点评估阶段，比预充电电压不同的电压。 因此，对于在预充电节点的状态响应提供信号的动态逻辑电路输出的包括（OUT 3）。 最后，动态逻辑电路包括电压保持电路（30KT1，30KT2），耦合到输出端，用于当在未启用条件放电路径的评估相位的一个实例的一部分期间耦合所述预充电电压施加到所述预充电节点 实例评估阶段。

公开(公告)号：EP1391813A1

公开(公告)日：2004-02-25

申请号：EP03102532.3

申请日：2003-08-13

申请人： Texas Instruments Incorporated

发明人： Bosshart, Patrick W.

IPC分类号： G06F9/38 ,  G06F9/302 ,  G06F9/305 ,  G06F9/315

CPC分类号： G06F9/3001 ,  G06F7/575 ,  G06F9/3828 ,  G06F9/3893

摘要： A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an integer number S of sub-units (54 1 , 54 2 , 54 3 ), wherein S is greater than one. Each of the sub-units is operable to execute, during an execution cycle, at least one of the instructions in the instruction set in response to at least two data arguments (A, B). The processor further comprises circuitry (58 A1 , 58 A2 , 58 A3 , 58 B1 , 58 B2 ) for providing an updated value of the at least two data arguments to less than all S of the sub-units for a single execution cycle.

摘要翻译： 处理器（50），其可操作以响应于指令集，其包括指令的多个。 所述处理器包括包含子单元（541，542，543）的整数S的功能单元（52），worin S是大于一。 每个子单元是可操作来执行，循环的执行期间，在响应设置为至少两个数据参数（A，B）的指令，指令中的至少一个。 所述处理器还用于在所述至少两个数据参数的更新值小于所有S子单元提供用于单次执行循环包括电路（58A1，58A2，58a3，58B1，58B2）。

公开(公告)号：EP1087529A3

公开(公告)日：2001-04-04

申请号：EP00308322.7

申请日：2000-09-22

申请人： Texas Instruments Incorporated

发明人： Bosshart, Patrick W. ,  Landman, Paul E.

IPC分类号： H03K19/00 ,  H03K19/096

CPC分类号： H03K19/0963

摘要： A domino logic circuit (18) comprising a first phase domino logic circuit (20) operable in a precharge phase and an evaluate phase. The first phase domino logic circuit comprises a precharge (20 PN ) node operable to change states. The domino logic circuit also comprises a second phase domino logic circuit (22) operable in a precharge phase and an evaluate phase, wherein the precharge phase and the evaluate phase of the first phase domino logic circuit are out of phase with respect to the precharge phase and an evaluate phase of the second phase domino logic circuit. Further, the second phase domino logic circuit comprises a precharge node (22 PN ) operable to change states in response to the states of the first phase domino logic circuit. Each of the first and second phase domino logic circuits further comprises a coupling device (20 PT , 22 PT ) which when conducting couples the precharge node to a precharge voltage during a precharge phase and a discharge path (20L, 20DT; 22L, 22DT) connected to the precharge node which when conducting couples the precharge node to a voltage different than the precharge voltage during an evaluate phase, wherein the discharge path comprises logic circuitry. The first phase domino logic circuit is operable such that the precharge node of the first phase domino logic circuit is charged to a first state during the precharge phase of the first phase domino logic circuit, and the precharge node of the first phase domino logic circuit conditionally changes to a second state during the evaluate phase of the first phase domino logic circuit. The second phase domino logic circuit is operable such that the state of the precharge node of the second phase domino logic circuit may change in the evaluate phase of the second phase domino logic circuit and in response to the first phase domino logic circuit only when the state of the precharge node of the first phase domino logic circuit did not change in an immediately preceding evaluate phase of the first phase domino logic circuit.