A method for generating charge sharing test vectors for a circuit is provided that includes providing an automatic test pattern generator operable to generate a first test vector (120) and a second test vector (122). The method further includes providing a test model (98) including a logic cell of a circuit and an auxiliary test circuit (100) where the auxiliary test circuit (100) includes a discharge AND gate (102) and a charge sharing AND gate (104). The method next provides for selecting an output of the discharge AND gate (104) as a target for a falling transition fault test vector generation by the automatic test pattern generator (124). The method next provides for generating a first test vector (120) for the test model (98) using the automatic test pattern generator (124) where the first test vector (120) provides an input pattern to discharge nodes of the logic cell. In addition, the discharge AND gate (102) evaluates to a logic level 1 for the first test vector (120). The method next provides for generating a second test vector (122) for the test model (98) using the automatic test pattern generator (124) where the second test vector (122) provides an input pattern to evoke the worst charge sharing behavior for the logic cell. In addition, the charge sharing AND gate (104) evaluates to a logic level 1 for the second test vector (122).