In the fabrication of a 0.10 micron CMOS integrated circuit (IC), a high-energy plasma etch is used to pattern a polysilicon layer (25) and an underlying gate oxide layer (23) to define gate structures. A thermal oxide step (S2) anneals silicon exposed and damaged by this etch. Instead of using this thermal oxide as a blocking layer for a source/drain extension implant, it is removed (S3) so as to expose the silicon surfaces of the source/drain regions. A TEOS deposition (S4) results in a carbon-bearing silicon dioxide layer (51) in contact with the surfaces of the crystalline source/drain regions. A boron PMOS source/drain extension implant (S5) is performed through this carbon-bearing blocking layer. Subsequent steps (S6-S9) result in the formation of sidewall spacers (71), heavily doped deep source/drain sections (91, 93), submetal dielectric (81), an intermetal dielectric interconnect structure, and passivation. The relatively high interstitial recombination rate of the carbon-bearing blocking layer attracts a flow of interstitial silicon. This flow draws some of the boron extension implant with it - effectively limiting the depth and lateral extension (under the gate) of the boron. This, in turn, helps limit the short-channel effect, and yields a more reliable 0.1 micron PMOS transistor.