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公开(公告)号：EP1297521A1
公开(公告)日：2003-04-02
申请号：EP01948433.6
申请日：2001-06-18
发明人： EVOY, David, R.
CPC分类号： G09G3/2018 , G09G3/3622 , G09G2320/0247
摘要： A method for providing intensity modulation for a display of an electronic device. The method uses tables of ratios for generating color modulation patterns. The method includes the step of defining a table of intensity values with each intensity value including a respective on-ratio and a respective off-ratio. A pixel intensity for a pixel of a display is selected by selecting a corresponding intensity value in the table. The pixel intensity is implemented by using an accumulator having an output for determining whether the pixel is on or off, wherein the pixel is on for zero and for positive values of the output and off for negative values of the output. The output is used to implement a duty cycle for the pixel, by turning the pixel on and off. The duty cycle is implemented by setting an initial output of the accumulator. The output is subsequently set to a value equal to the output minus the off-ratio if the pixel is on, and setting the output to the output plus the on-ratio if the pixel is off. Successively turning the pixel on and off in accordance with the output thereby implements a duty cycle for the pixel according to the on-ratio and off-ratio of the intensity value.
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公开(公告)号：EP1297430A2
公开(公告)日：2003-04-02
申请号：EP01906724.8
申请日：2001-01-26
IPC分类号： G06F13/00
CPC分类号： G06F13/4226
摘要： A data transaction access system for an embedded microprocessor coupled to a PCMCIA bus device. A bus master and a host bus adapter are couple d to a local bus for enabling communication between the bus master and a PCMCIA device. The PCMCIA device is coupled to the host bus adapter via a PCMCIA bus. The bus master uses the local bus to communicate with the PCMCIA device via the host bus adapter. A wait register is coupled to the host bus adapter to receive a delay input from the PCMCIA device describing a latency period of the device when completing a data transaction. Where the latency period described by the delay input is less than a predetermined amount, the host bus adapter is configured to insert wait states into the data transaction of the bus master. When the latency period is greater than the predetermined amount, the host bus adapter is configured to retry the data transaction of the bus master. Alternatively, the wait register is adapted to couple the delay input to the bus master such that the bus master initiates a subsequent access to the PCMCIA device at the expiration of the latency period in order to efficiently complete the subsequent access to the target PCI agent. Alternatively, the wait register is coupled to an arbiter such that the arbiter does not grant the local bus to the bus master for a subsequent access until the expiration of the latency period.
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公开(公告)号：EP1259165A2
公开(公告)日：2002-11-27
申请号：EP00992873.0
申请日：2000-12-07
发明人： HAYEM, Frederic , ARNOULD, Patrick
IPC分类号： A61B8/00
CPC分类号： G01R31/318342
摘要： A method of operating on a net-list describing an integrated circuit design for use with an automated test pattern generator for testing an integrated circuit built using the design is described. The method includes replacing a defective portion of the design in test mode with a substitute circuit to reduce testing impact of the defective portion. The method includes identifying a first defective portion of the integrated circuit design in the net-list, determining conditions under which the first defective portion is likely to malfunction and replacing the first defective portion in the net-list with another first portion that provides unknown output signals representing an unknown state in response to conditions under which the first defective portion is likely to malfunction.
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公开(公告)号：EP1144155A3
公开(公告)日：2002-09-11
申请号：EP00959642.0
申请日：2000-08-30
IPC分类号： B24B1/00
CPC分类号： B24B53/017 , B24B1/04 , B24B41/061 , B24B57/02
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5.发明公开METHOD AND SYSTEM FOR EFFICIENTLY COMPUTING A NUMBER OF INTEGRATED CIRCUIT DIES 审中-公开方法和系统的身份证号码的有效计算
公开(公告)号：EP1210731A2
公开(公告)日：2002-06-05
申请号：EP00989646.5
申请日：2000-10-02
CPC分类号： G03F7/70433
摘要： A method and system thereof for efficiently computing the number of dies per wafer and the corresponding number of stepper shots. Dimensions for a die and the size of the wafer are received. The dimensions comprise a die element size that is a function of a scribe lane width, a guard ring width, an input/output pad area, and a length and a width of the die. A die count lookup table is selected for the specified wafer size and used to determine the die count corresponding to the die element size. In a similar manner, a stepper shot count lookup table is selected for the specified wafer size and used to determine the stepper shot count corresponding to the die element size. Because the die element size accounts for the different production parameters, a die count lookup table and a stepper shot count lookup table need to exist only for each wafer size, significantly reducing the number of required lookup tables and correspondingly reducing the amount of storage space and maintenance required.
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6.发明公开
公开(公告)号：EP1208594A2
公开(公告)日：2002-05-29
申请号：EP00992860.7
申请日：2000-12-06
IPC分类号： H01L21/762
CPC分类号： H01L21/76235
摘要： An isolation structure on an integrated circuit is formed using a shallow trench (51) isolation process. On a substrate (10), a trench (51) is formed. A thermal anneal is performed to oxidize exposed areas of the substrate (10) to provide for round corners (42) at a perimeter of the trench (51). The thermal anneal is perfomed in an ambient where a chlorine source is added to O2 in order to minimize facets while creating the round corners (42). Oxidation time is lengthened by introducing an inert gas during the thermal anneal.
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公开(公告)号：EP1166346A1
公开(公告)日：2002-01-02
申请号：EP00986720.1
申请日：2000-12-22
发明人： ZHENG, Tammy
IPC分类号： H01L21/3213
CPC分类号： H01L21/32137 , H01L21/28123
摘要： Semiconductor chip manufacturing is enhanced using a highly selective etching process that enables the formation of structure having near 90° side walls within the chip without degrading the selectivity. According to an example embodiment of the present invention, a plasma generated from an etch gas and an inert gas is used to etch a semiconductor chip having substrate formed over a thin oxide. The chip is etched at an etch pressure and plasma power that, when coupled with the etch gas chemistry, are sufficient to achieve high oxide selectivity. The inert gas supplied concurrently with the etch gas is sufficient to maintain an about vertical side wall profile of the substrate as it is etched without degrading the etch gas selectivity.
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公开(公告)号：EP1166342A1
公开(公告)日：2002-01-02
申请号：EP00989595.4
申请日：2000-12-29
发明人： YEH, Edward
IPC分类号： H01L21/311
CPC分类号： H01L21/31138 , G03F7/42
摘要： Photoresist removal from a semiconductor chip is enhanced via a method and system that remove photoresist without causing photoresist popping and without causing undesirable etching of other structures on the chip. According to an example embodiment of the present invention, a photoresist mask layer formed on the substrate of a semiconductor wafer is used as a mask for etching a portion f the substrate. The semiconductor wafer is then ashed and an upper portion of the photoresist layer is removed that would otherwise pop and leave residue on the wafer. The remaining photoresist can then be removed in a conventional high-temperature asher.
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公开(公告)号：EP1145309A3
公开(公告)日：2001-12-12
申请号：EP00972400.6
申请日：2000-09-07
IPC分类号： H01L23/495 , H01L23/498
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10.发明公开
公开(公告)号：EP1151565A1
公开(公告)日：2001-11-07
申请号：EP00963366.0
申请日：2000-09-12
发明人： GRUNERT, Norbert
CPC分类号： H04L1/205 , H04L7/0012 , H04L7/02
摘要： A method and system for reducing data loss in digital communication between asynchronous digital devices. The method includes generating a first data transmission stream using a transmitter device, the first data stream synchronous to a first clock signal. A second data transmission stream is then generated using the transmitter device, wherein the second data transmission stream is a copy of the first data stream with a phase shift. A determination is then made as to whether the phase of the first clock signal is within a predetermined amount of the phase of a receiver clock signal of a receiver device, wherein the receiver clock signal is used by the receiver device to sample received data. The first data stream is transmitted to the receiver device when the phase of the first clock signal differs from the phase of the second clock signal by greater than the predetermined amount. The second data stream is transmitted to the receiver device when the phase of the first clock signal differs from the phase of the receiver clock signal by less than the predetermined amount such that jitter on the first clock signal and the receiver clock signal does not disrupt communication between the transmitter device and the receiver device.
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