A semiconductor memory device, divided into a plurality of memory cell blocks (Block 0-3) in accordance with a row address. Each memory cell block has a memory cell array (MC), a redundant memory cell array (RMC) and a word driver (WDR) driving the memory cell array. A redundancy decision circuit (50) is provided for deciding whether or not a supplied address corresponds to a recorded redundant address. The memory cell array (MC) and redundant memory cell array (RMC) are divided into a plurality of arrays (10L, 10R, 12L, 12R) in the column direction, and the divided plural memory cell arrays and the redundant memory cell arrays output data (DQ) to the outside together. A substitution data holding circuit (71-74) for holding substitution data indicating substitution/non-substitution by a redundant memory cell for each memory cell array divided in the column direction is provided. When a non-defective cell is selected, the word drivers (14L, 14R) drive word lines in the divided plural memory cell arrays (10L, 10R) simultaneously according to the row address. On the other hand, when a defective cell is selected, the word drivers (14L, 4R) drive any one of the word lines of the memory cell array (10L, 10R) or the redundant memory cell array (12L, 12R) respectively for the divided plural arrays, in accordance with the output of the redundancy decision circuit (50) and the output of the substitution data holding circuit (71-74). In this way, a part of the data being output externally is capable to be exchanged from the memory cell array (10L, 10R) into the redundant memory cell array (12L, 12R).