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    Semiconductor memory
    2.
    发明公开
    Semiconductor memory 有权
    半导体内存

    公开(公告)号：EP1288961A2

    公开(公告)日：2003-03-05

    申请号：EP02252317.9

    申请日：2002-03-28

    申请人： FUJITSU LIMITED

    发明人： Yamaguchi, Shusaku ,  Uchida, Toshiya ,  Yagishita, Yoshimasa ,  Bando, Yoshihide ,  Yada, Masahiro ,  Okuda, Masaki ,  Kobayashi, Hiroyuki ,  Hara, Kota ,  Fujioka, Shinya ,  Fujieda, Waichiro

    IPC分类号： G11C11/406

    CPC分类号： G11C7/1006 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4087 ,  G11C2211/4061 ,  G11C2211/4062

    摘要： A semiconductor memory is provided with a plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command (WRA) and the refresh command (REFRQ) conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

    摘要翻译： 半导体存储器具有用于再现第一存储块的数据的多个第一存储块和第二存储块。 当读取命令和刷新命令彼此冲突时，读取控制电路根据刷新命令访问第一存储器块，并通过使用第二存储器块再现读取数据。 当写入命令（WRA）和刷新命令（REFRQ）彼此冲突时，写入控制电路根据命令接收的顺序操作存储器块。 因此，可以在不被用户识别的情况下执行刷新操作。 即，可以提供用户友好的半导体存储器。

    Command input circuit
    3.
    发明公开
    Command input circuit 审中-公开
    输入控制信号电路

    公开(公告)号：EP1233417A3

    公开(公告)日：2004-01-07

    申请号：EP01310107.6

    申请日：2001-12-03

    申请人： FUJITSU LIMITED

    发明人： Uchida, Toshiya

    IPC分类号： G11C7/10 ,  G11C7/22

    CPC分类号： G11C7/109 ,  G11C7/1066 ,  G11C7/1078

    摘要： In a command input circuit: m command acquisition units (112 to 115) are provided corresponding to first to mth commands, respectively, where m is an integer greater than one; a clock signal supplying unit (100) supplies n clock signals respectively having different phases to the m command acquisition units (112 to 115), where n is an integer greater than one; and a command input unit (110, 130) receives said first to mth commands, and supplies the first to mth commands to the m command acquisition units (112 to 115). Each of the m command acquisition units acquires one of the first to mth commands corresponding to the command acquisition unit in response to one of m edges of the n clock signals corresponding to the one of the first to mth commands. The processing unit performs processing in accordance with the first to mth commands.

    Semiconductor memory device with redundancy
    4.
    发明公开
    Semiconductor memory device with redundancy 失效
    Halbleiterspeicheranordnung mit Redundanz

    公开(公告)号：EP0881571A1

    公开(公告)日：1998-12-02

    申请号：EP97309160.6

    申请日：1997-11-13

    申请人： FUJITSU LIMITED

    发明人： Kojima, Kazumi, c/o Fujitsu VLSI Ltd. ,  Uchida, Toshiya

    IPC分类号： G06F11/20

    CPC分类号： G11C29/789 ,  G11C29/70 ,  G11C29/808

    摘要： A semiconductor memory device comprising a memory cell array (10) and a redundant memory cell array (12) in which a defective cell in the memory cell array is substituted by a cell in the redundant memory cell array; further comprising: a PROM circuit (46) in which a redundant address corresponding to the defective cell is recorded; a redundant address data holding circuit (48) that holds the data of the redundant address recorded in the PROM circuit (46) on initialisation; a circuit (50) for deciding on redundancy that compares the data held by the redundant address data holding circuit (48) with an address supplied from outside and makes a decision; and a driver circuit (14) for the memory cell array that is actuated in accordance with the result of this decision by the circuit for deciding on redundancy and a driver circuit (16) for the redundant memory cell array. Since a semiconductor memory device as above does not have a PROM circuit that delays the operation in the circuit for deciding on redundancy, high-speed operation of the circuit for deciding on redundancy can be achieved. As a result, overall access time can be reduced.

    摘要翻译： 一种半导体存储器件，包括存储单元阵列（10）和冗余存储单元阵列（12），其中所述存储单元阵列中的缺陷单元被所述冗余存储单元阵列中的单元代替; 进一步包括：PROM电路（46），其中记录与所述有缺陷单元相对应的冗余地址; 冗余地址数据保持电路（48），其在初始化时保存记录在PROM电路（46）中的冗余地址的数据; 用于决定将由冗余地址数据保持电路（48）保持的数据与从外部提供的地址进行比较的冗余判定的电路（50） 以及用于根据该决定的结果被驱动以用于确定冗余的存储单元阵列的驱动器电路（14）和用于冗余存储单元阵列的驱动器电路（16）。 由于如上所述的半导体存储器件不具有延迟用于决定冗余的电路中的操作的PROM电路，所以可以实现用于决定冗余的电路的高速操作。 结果，整体访问时间可以减少。

    Semiconductor memory device
    6.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP1191543A3

    公开(公告)日：2002-08-14

    申请号：EP01126502.2

    申请日：1997-11-13

    申请人： FUJITSU LIMITED

    发明人： Kojima, Kazumi ,  Uchida, Toshiya

    IPC分类号： G11C29/00

    CPC分类号： G11C29/789 ,  G11C29/70 ,  G11C29/808

    摘要： A semiconductor memory device, divided into a plurality of memory cell blocks (Block 0-3) in accordance with a row address. Each memory cell block has a memory cell array (MC), a redundant memory cell array (RMC) and a word driver (WDR) driving the memory cell array. A redundancy decision circuit (50) is provided for deciding whether or not a supplied address corresponds to a recorded redundant address. The memory cell array (MC) and redundant memory cell array (RMC) are divided into a plurality of arrays (10L, 10R, 12L, 12R) in the column direction, and the divided plural memory cell arrays and the redundant memory cell arrays output data (DQ) to the outside together. A substitution data holding circuit (71-74) for holding substitution data indicating substitution/non-substitution by a redundant memory cell for each memory cell array divided in the column direction is provided. When a non-defective cell is selected, the word drivers (14L, 14R) drive word lines in the divided plural memory cell arrays (10L, 10R) simultaneously according to the row address. On the other hand, when a defective cell is selected, the word drivers (14L, 4R) drive any one of the word lines of the memory cell array (10L, 10R) or the redundant memory cell array (12L, 12R) respectively for the divided plural arrays, in accordance with the output of the redundancy decision circuit (50) and the output of the substitution data holding circuit (71-74). In this way, a part of the data being output externally is capable to be exchanged from the memory cell array (10L, 10R) into the redundant memory cell array (12L, 12R).

    摘要翻译： 根据行地址划分成多个存储单元块（块0-3）的半导体存储器件。 每个存储单元块具有存储单元阵列（MC），冗余存储单元阵列（RMC）和驱动存储单元阵列的字驱动器（WDR）。 冗余判定电路（50）被提供用于判定提供的地址是否对应于记录的冗余地址。 存储单元阵列（MC）和冗余存储单元阵列（RMC）在列方向上被分成多个阵列（10L，10R，12L，12R），并且分割后的多个存储单元阵列和冗余存储单元阵列输出 数据（DQ）一起发送到外部。 提供了用于保持替代数据的替代数据保持电路（71-74），该替代数据指示用于在列方向上划分的每个存储器单元阵列的冗余存储器单元的替换/不替换。 当选择无缺陷单元时，字驱动器（14L，14R）根据行地址同时驱动划分的多个存储单元阵列（10L，10R）中的字线。 另一方面，当选择缺陷单元时，字驱动器（14L，4R）分别驱动存储单元阵列（10L，10R）或冗余存储单元阵列（12L，12R）的字线中的任何一个， 根据冗余判定电路（50）的输出和替代数据保持电路（71-74）的输出，对分割后的多个阵列进行编码。 以这种方式，从外部输出的一部分数据能够从存储单元阵列（10L，10R）交换到冗余存储单元阵列（12L，12R）。

    Command input circuit
    8.
    发明公开
    Command input circuit 审中-公开
    Eingangssteuersignalschaltung

    公开(公告)号：EP1233417A2

    公开(公告)日：2002-08-21

    申请号：EP01310107.6

    申请日：2001-12-03

    申请人： FUJITSU LIMITED

    发明人： Uchida, Toshiya

    IPC分类号： G11C7/10

    CPC分类号： G11C7/109 ,  G11C7/1066 ,  G11C7/1078

    摘要： In a command input circuit: m command acquisition units (112 to 115) are provided corresponding to first to mth commands, respectively, where m is an integer greater than one; a clock signal supplying unit (100) supplies n clock signals respectively having different phases to the m command acquisition units (112 to 115), where n is an integer greater than one; and a command input unit (110, 130) receives said first to mth commands, and supplies the first to mth commands to the m command acquisition units (112 to 115). Each of the m command acquisition units acquires one of the first to mth commands corresponding to the command acquisition unit in response to one of m edges of the n clock signals corresponding to the one of the first to mth commands. The processing unit performs processing in accordance with the first to mth commands.

    摘要翻译： 在命令输入电路中：分别对应于第一至第m个命令提供m个命令获取单元（112至115），其中m是大于1的整数; 时钟信号提供单元（100）向m个命令获取单元（112-115）提供分别具有不同相位的n个时钟信号，其中n是大于1的整数; 并且命令输入单元（110,130）接收所述第一至第m命令，并将所述第一至第m命令提供给所述m个命令获取单元（112至115）。 响应于与第一至第m命令中的一个对应的n个时钟信号的m个边沿之一，m个命令获取单元中的每一个获取与命令获取单元相对应的第一至第m命令之一。 处理单元根据第一至第m命令执行处理。

    Semiconductor memory device
    9.
    发明公开
    Semiconductor memory device 失效
    Halbleiterspeicheranordnung

    公开(公告)号：EP1191543A2

    公开(公告)日：2002-03-27

    申请号：EP01126502.2

    申请日：1997-11-13

    申请人： FUJITSU LIMITED

    发明人： Kojima, Kazumi ,  Uchida, Toshiya

    IPC分类号： G11C29/00

    CPC分类号： G11C29/789 ,  G11C29/70 ,  G11C29/808

    摘要： A semiconductor memory device, divided into a plurality of memory cell blocks (Block 0-3) in accordance with a row address. Each memory cell block has a memory cell array (MC), a redundant memory cell array (RMC) and a word driver (WDR) driving the memory cell array. A redundancy decision circuit (50) is provided for deciding whether or not a supplied address corresponds to a recorded redundant address. The memory cell array (MC) and redundant memory cell array (RMC) are divided into a plurality of arrays (10L, 10R, 12L, 12R) in the column direction, and the divided plural memory cell arrays and the redundant memory cell arrays output data (DQ) to the outside together. A substitution data holding circuit (71-74) for holding substitution data indicating substitution/non-substitution by a redundant memory cell for each memory cell array divided in the column direction is provided. When a non-defective cell is selected, the word drivers (14L, 14R) drive word lines in the divided plural memory cell arrays (10L, 10R) simultaneously according to the row address. On the other hand, when a defective cell is selected, the word drivers (14L, 4R) drive any one of the word lines of the memory cell array (10L, 10R) or the redundant memory cell array (12L, 12R) respectively for the divided plural arrays, in accordance with the output of the redundancy decision circuit (50) and the output of the substitution data holding circuit (71-74). In this way, a part of the data being output externally is capable to be exchanged from the memory cell array (10L, 10R) into the redundant memory cell array (12L, 12R).

    摘要翻译： 一种半导体存储器件，根据行地址被分成多个存储单元块（块0-3）。 每个存储单元块具有存储单元阵列（MC），冗余存储单元阵列（RMC）和驱动存储单元阵列的字驱动器（WDR）。 提供冗余判定电路（50），用于判定所提供的地址是否对应于记录的冗余地址。 存储单元阵列（MC）和冗余存储单元阵列（RMC）在列方向上被分成多个阵列（10L，10R，12L，12R），分割的多个存储单元阵列和冗余存储单元阵列输出 数据（DQ）到外面一起。 提供了一种替代数据保持电路（71-74），用于保存指示在列方向上划分的每个存储单元阵列的冗余存储单元的替代/不替代的替换数据。 当选择无缺陷单元时，字驱动器（14L，14R）根据行地址同时驱动划分的多个存储单元阵列（10L，10R）中的字线。 另一方面，当选择有缺陷的单元时，字驱动器（14L，4R）分别驱动存储单元阵列（10L，10R）或冗余存储单元阵列（12L，12R）中的任何一条字线用于 根据冗余判定电路（50）的输出和替代数据保持电路（71-74）的输出，分割的多个阵列。 以这种方式，外部输出的一部分数据能够从存储单元阵列（10L，10R）交换到冗余存储单元阵列（12L，12R）中。