A method and apparatus for simultaneously recording and displaying video signals from two different video sources. The apparatus comprises a main channel processing circuit/logic (148), a second channel processing circuit/logic (150), and common circuitry/logic (152). The common circuitry comprises a digital video encoder pipe (112) that decodes both a first and second encoded video signals. The main channel processing circuit processes a first decoded video signal utilizing a first clock to form a main picture for display. The second channel processing circuit processes a second decoded video signal to form a PIP picture for combination with the main picture for display. The PIP picture is produced using a second clock signal that is independent from the first clock signal. In a record mode, the second channel clock is coupled to the second channel processing circuit to produce a recordable signal using a digital encoder. The recordable signal also forms the PIP picture that is coupled to the main channel processing circuit to produce a PIP picture that is used to monitor the recording process.