A method of manufacturing one or more trench DMOS transistors is provided. In this method, one or more body regions (204) adjacent one or more trenches (207) are provided. The one or more trenches are lined with a first insulating layer (206). A portion of the first insulating layer is removed along at least the upper sidewalls of the trenches, exposing portions (204a) of the body regions. An oxide layer (209) is then formed over at least the exposed portions of the body regions, resulting in regions of reduced majority carrier concentration within the body regions adjacent the oxide layer. This modification of the majority carrier concentration in the body regions is advantageous in that a low threshold voltage can be established within the DMOS transistor without resorting to a thinner gate oxide (which would reduce yield and switching speed) and without substantially increasing the likelihood of punch-through.