公开(公告)号：EP1346417B1

公开(公告)日：2006-03-29

申请号：EP01991246.8

申请日：2001-12-13

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： HSHIEH, Fwu-Iuan ,  SO, Koon, Chong ,  AMATO, John, E.

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/66143 ,  H01L29/417 ,  H01L29/872

摘要： A trench Schottky barrier rectifier and a method of making the same are disclosed. The rectifier comprises: (a) A semiconductor region having first and second opposing faces. The semiconductor region comprises a drift region of first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face. The drift region and a lower net doping concentration than that of the cathode region. (b) A plurality of trenches extending into the semiconductor region from the first face. The trenches define a plurality of mesas within the semiconductor region, and the trenches form a plurality of trench intersections. (c) An oxide layer covering the semiconductor region on bottoms of the trenches and on lower portions of sidewalls of the trenches. (d) A polysilicon region disposed over the oxide layer within the trenches. (e) Insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.

公开(公告)号：EP1483791A1

公开(公告)日：2004-12-08

申请号：EP03711525.0

申请日：2003-03-11

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： SO, Koon, Chong ,  HSHIEH, Fwu-Iuan ,  TSUI, Yan, Man

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/7811

摘要： A trench DMOS transistor cell is provided that includes a substrate of a first conductivity type and a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and a conductive electrode is placed in the trench overlying the insulating layer. A source region of the first conductivity type is located in the body region adjacent to the trench. The trench has sidewalls that define a polygon in the plane of the substrate so that adjacent sidewalls contact one another at an angle greater than 90 degrees.

公开(公告)号：EP1314203A2

公开(公告)日：2003-05-28

申请号：EP01964490.5

申请日：2001-08-29

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： HSHIEH, Fwu-Iuan ,  SO, Koon, Chong ,  TSUI, Yan Man

IPC分类号： H01L29/00

CPC分类号： H01L29/7813 ,  H01L29/4238 ,  H01L2924/0002 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

摘要： A trench MOSFET includes a plurality of trench segments in an upper surface of an epitaxial layer, extending through a second conductivity type region into a first conductivity type epitaxial region, segment at least partially separated from an adjacent segment by a terminating region, and the trench segments defining a plurality of polygonal body regions within the second conductivity type. A first insulating layer at least partially lines each trench and a plurality of first conductive regions are provided within the trench segments adjacent to the first layer. Each of the conductive regions is connected to an adjacent first conductive region by a connecting conductive region, overlying the terminating region, that bridges at least one of the terminating regions and a plurality of first conductivity type source regions are within upper portions of the polygonal body regions and adjacent the trench segments, the source regions positioned outside the terminating regions.

公开(公告)号：EP1266406A2

公开(公告)日：2002-12-18

申请号：EP01910706.9

申请日：2001-02-15

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： HSHIEH, Fwu-Iuan ,  SO, Koon Chong ,  TSUI, Yan Man

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7813 ,  H01L29/0626 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/7811

摘要： A trench DMOS transistor structure (200) is provided that includes at least three individual trench DMOS transistor cells (21) formed on a substrate (220) of a first conductivity type. The plurality of individual DMOS transistor cells is dividable into peripheral transistor cells and interior transistor cells. Each of the individual transistor cells includes a body region (214) located on the substrate, which has a second conductivity type. At least one trench (202,204) extends through the body region and the substrate. An insulating layer (230) lines the trench. A conductive electrode is located in the trench, which overlies the insulating layer. Interior transistor cells, but not the peripheral transistor cells, each further include a source region (240) of the first conductivity type in the body region adjacent to the trench. The body regions of the peripheral transistor cells are more lightly doped than the body regions of the interior transistor cells.

公开(公告)号：EP1314203B1

公开(公告)日：2007-01-03

申请号：EP01964490.5

申请日：2001-08-29

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： HSHIEH, Fwu-Iuan ,  SO, Koon, Chong ,  TSUI, Yan Man

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/4238 ,  H01L2924/0002 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

摘要： A trench MOSFET includes a plurality of trench segments in an upper surface of an epitaxial layer, extending through a second conductivity type region into a first conductivity type epitaxial region, segment at least partially separated from an adjacent segment by a terminating region, and the trench segments defining a plurality of polygonal body regions within the second conductivity type. A first insulating layer at least partially lines each trench and a plurality of first conductive regions are provided within the trench segments adjacent to the first layer. Each of the conductive regions is connected to an adjacent first conductive region by a connecting conductive region, overlying the terminating region, that bridges at least one of the terminating regions and a plurality of first conductivity type source regions are within upper portions of the polygonal body regions and adjacent the trench segments, the source regions positioned outside the terminating regions.

公开(公告)号：EP1468453A2

公开(公告)日：2004-10-20

申请号：EP02806284.2

申请日：2002-12-30

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： BLANCHARD, Richard, A. ,  HSHIEH, Fwu-Iuan

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/223 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/66712

摘要： A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. At least one doped column having a dopant of a second conductivity type is located in the epitaxial layer, adjacent a sidewall of the trench. The trench is etched using an etchant gas that also serves as a dopant source for the formation of the doped column. For example, if a p-type dopant such as boron is desired, BCl3 may be used as the etchant gas. Alternatively, if an n-type dopant such as phosphorus is required, PH3 may be used as the etchant gas. The dopant present in the gas is incorporated into the silicon defining the surfaces of the trench. This dopant is subsequently diffused to form the doped column surrounding the trench. The trench is filled with an insulating material such as silicon dioxide, silicon nitride, polysilicon, or a combination of such materials. The step of filling the trench may be performed before or after the dopant is diffused to form the doped column. Finally, at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

公开(公告)号：EP1292990A2

公开(公告)日：2003-03-19

申请号：EP01944581.6

申请日：2001-06-14

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： HSHIEH, Fwu-Iuan ,  SO, Koon, Chong

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/7811

摘要： A trench MOSFET device and process for making the same are described. The trench MOSFET has a substrate of a first conductivity type, an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate, a plurality of trenches within the epitaxial layer, a first insulating layer, such as an oxide layer, lining the trenches, a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer, and one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions. Each trench body region and each termination body region has a first region of a second conductivity type, the second conductivity type being opposite the first conductivity type, and a second region of the second conductivity type adjacent the first region, the second region having a greater majority carrier concentration than the first region, and the second region being disposed above the first region and adjacent and extending to an outer wall of each of the plurality of trenches. A plurality of source regions of the first conductivity type are positioned adjacent the trenches within upper portions the trench body regions.

公开(公告)号：EP1269530A2

公开(公告)日：2003-01-02

申请号：EP01920447.8

申请日：2001-03-16

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： SO, Koon, Chong ,  HSHIEH, Fwu-Iuan

IPC分类号： H01L21/336

CPC分类号： H01L29/1095

摘要： A method of manufacturing one or more trench DMOS transistors is provided. In this method, one or more body regions (204) adjacent one or more trenches (207) are provided. The one or more trenches are lined with a first insulating layer (206). A portion of the first insulating layer is removed along at least the upper sidewalls of the trenches, exposing portions (204a) of the body regions. An oxide layer (209) is then formed over at least the exposed portions of the body regions, resulting in regions of reduced majority carrier concentration within the body regions adjacent the oxide layer. This modification of the majority carrier concentration in the body regions is advantageous in that a low threshold voltage can be established within the DMOS transistor without resorting to a thinner gate oxide (which would reduce yield and switching speed) and without substantially increasing the likelihood of punch-through.

公开(公告)号：EP1454360A1

公开(公告)日：2004-09-08

申请号：EP02782334.3

申请日：2002-11-20

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： HSHIEH, Fwu-Iuan ,  SO, Koon, Chong ,  AMATO, John, E. ,  TSUI, Yan, Man

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/74 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/8238 ,  H01L21/4763 ,  H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/0878

摘要： A method of forming a trench MOSFET device includes depositing an epitaxial layer over a substrate, both having the first conductivity type, the epitaxial layer having a lower majority carrier concentration than the substrate, forming a body region of a second conductivity type within an upper portion of the epitaxial layer, etching a trench extending into the epitaxial layer from an upper surface of the epitaxial layer, the trench extending to a greater depth from the upper surface of the epitaxial layer than the body region, forming a doped region of the first conductivity type between a bottom portion of the trench and substrate, the doped region having a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer, wherein the doped region is diffused and spans 100% of the distance from the trench bottom portion to the substrate, forming an insulating layer lining at least a portion of the trench, forming a conductive region within the trench adjacent the insulating layer and forming a source region of said first conductivity type within an upper portion of the body region and adjacent the trench.

摘要翻译： 形成沟槽MOSFET器件的方法包括在衬底上沉积外延层，二者具有第一导电类型，外延层具有比衬底更低的载流子浓度，在上部形成第二导电类型的体区 从外延层的上表面蚀刻延伸到外延层中的沟槽，沟槽从外延层的上表面延伸到比体区更大的深度，形成第一导电性的掺杂区域 类型在沟槽的底部和衬底之间，掺杂区域具有比衬底的载流子浓度低的多数载流子浓度，并且高于外延层的掺杂区域，其中掺杂区域扩散并跨越距离的距离的100％ 沟槽底部到衬底，形成衬里至少一部分沟槽的绝缘层，形成导电区域wi 在相邻于绝缘层的沟槽之间变薄，并且在本体区域的上部并且与沟槽相邻的区域内形成所述第一导电类型的源极区域。

公开(公告)号：EP1393379A1

公开(公告)日：2004-03-03

申请号：EP02739587.0

申请日：2002-05-31

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： HSHIEH, Fwu-Iuan ,  SO, Koon, Chong

IPC分类号： H01L29/47

CPC分类号： H01L29/417 ,  H01L27/0817 ,  H01L27/095 ,  H01L29/42364 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/8725

摘要： a schottky rectifier is provided. The Schottky rectifier comprises: (A) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region (12C) of first conductivity type adjacent the first face (12A) and a drift region(12D) of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (B) one or more trenches extending from the second face (12B) into the semiconductor region and defining one or more mesas (14) within the semiconductor region; (C) an insulating region (16) adjacent the semiconductor region in lower portions of the trench; (D) and an anode electrode (18) that is (I) adjacent to and forms a schottky rectifying contact with the semiconductor at the second face (12), (II) adjacent to and forms a schottky rectifying contact with the semiconductor region within upper portions of the trench and (III) adjacent to the insulating region (16) within the lower portions of the trench.

摘要翻译： 提供肖特基整流器。 肖特基整流器包括：（A）具有第一和第二相对面的半导体区域，其中半导体区域包括与第一面（12A）相邻的第一导电类型的阴极区域（12C）和第一导电类型的第一漂移区域 所述漂移区具有比所述阴极区域的净掺杂浓度低的导电类型，并且所述漂移区域具有比所述阴极区域低的净掺杂浓度; （B）从所述第二面（12B）延伸到所述半导体区域中并且在所述半导体区域内限定一个或多个台面（14）的一个或多个沟槽; （C）在所述沟槽的下部中与所述半导体区域相邻的绝缘区域（16）; （D）和阳极电极（18），所述阳极电极（18）在所述第二面（12）处与所述半导体相邻且与所述半导体形成肖特基整流接触，所述第二面与所述半导体区域相邻且与所述半导体区域形成肖特基整流接触 沟槽的上部和（III）与沟槽的下部内的绝缘区域（16）相邻。