A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines (17) in trenches in an insulation (oxide) layer (12) of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer (15) disposed on the oxide layer (12) and having a lower portion located in the trenches (13) for forming metal lines and an upper portioN (18) overlying the lower portion (16). The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion (18) while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion (18) without dishing of the metal layer lower portion (16) in the trenches (13). The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion (18) with minimized (reduced) dishing of the metal layer lower portion (16) to an extent providing the metal lines (17) as individual metal lines (17) in the trenches (13). Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.