公开(公告)号：EP1279188A1

公开(公告)日：2003-01-29

申请号：EP01935012.3

申请日：2001-05-02

申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

发明人： WANG, Yun-Yu ,  JAMMY, Rajarao ,  KIMBALL, Lee, J. ,  KOTECKI, David, E. ,  LIAN, Jenny ,  LIN, Chenting ,  MILLER, John, A. ,  NAGEL, Nicholas ,  SHEN, Hua ,  WILDMAN, Horatio, S.

IPC分类号： H01L21/02

CPC分类号： H01L28/75 ,  H01L28/55 ,  H01L28/60

摘要： A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second electrode portion is provided.

公开(公告)号：EP1281199A2

公开(公告)日：2003-02-05

申请号：EP01937301.8

申请日：2001-05-10

申请人： Infineon Technologies North America Corp.

发明人： LIN, Chenting ,  PLOESSL, Robert

IPC分类号： H01L21/321

CPC分类号： H01L21/3212 ,  H01L21/7684

摘要： A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines (17) in trenches in an insulation (oxide) layer (12) of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer (15) disposed on the oxide layer (12) and having a lower portion located in the trenches (13) for forming metal lines and an upper portioN (18) overlying the lower portion (16). The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion (18) while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion (18) without dishing of the metal layer lower portion (16) in the trenches (13). The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion (18) with minimized (reduced) dishing of the metal layer lower portion (16) to an extent providing the metal lines (17) as individual metal lines (17) in the trenches (13). Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.

公开(公告)号：EP1281199B1

公开(公告)日：2007-02-21

申请号：EP01937301.8

申请日：2001-05-10

申请人： Infineon Technologies North America Corp.

发明人： LIN, Chenting ,  PLOESSL, Robert

IPC分类号： H01L21/321

CPC分类号： H01L21/3212 ,  H01L21/7684

摘要： A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines in trenches in an insulation (oxide) layer of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion without dishing of the metal layer lower portion in the trenches. The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion with minimized (reduced) dishing of the metal layer lower portion to an extent providing the metal lines as individual metal lines in the trenches. Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.

公开(公告)号：EP1346401A2

公开(公告)日：2003-09-24

申请号：EP01995905.5

申请日：2001-11-14

申请人： Infineon Technologies North America Corp.

发明人： LIAN, Jingyu ,  LIN, Chenting ,  NAGEL, Nicolas ,  WISE, Michael

IPC分类号： H01L21/02

CPC分类号： H01L28/75 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  Y10S257/906 ,  Y10S257/908

摘要： A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.

公开(公告)号：EP1292977A2

公开(公告)日：2003-03-19

申请号：EP01946617.6

申请日：2001-06-21

申请人： Infineon Technologies North America Corp.

发明人： WEBER, Stefan ,  RUF, Alexander ,  LIN, Chenting ,  KNORR, Andreas

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/28568 ,  H01L21/76807 ,  H01L21/76871 ,  H01L21/76877

摘要： A method for forming metallizations for semiconductor devices, in accordance with the present invention, includes forming trenches (107) in a dielectric layer (104), depositing a single layer diffusion barrier (116) in the trenches, and without an air-brake, depositing a seed layer (118) of metal on the surface of the diffusion barrier. The trenches are then filled with metal (120). The metal adheres to the seed layer, which adheres to the diffusion barrier to provide many improvements in electrical characteristics as well as to reduce failures in the semiconductor devices.