A memory cell in a DRAM, which is a semiconductor memory device, is provided with a bit line 21a connected to a bit line plug 20b and a local interconnect 21b , over a first interlevel insulating film 18 . A conductor sidewall 40 of TiAIN is formed on side faces of hard mask 37, upper barrier metal 36, Pt film 35 and BST film 34. No contact hole is provided on the Pt film 35 constituting an upper electrode 35a . The upper electrode 35a is connected to an upper interconnect (a Cu interconnect 42 ) via the conductor sidewall 40 , dummy lower electrode 33b , dummy cell plug 30 and local interconnect 21b . The Pt film 35 is not exposed to a reducing atmosphere, and therefore deterioration in characteristics of the capacitive insulating film 34a can be prevented.