公开(公告)号：EP1475839A1

公开(公告)日：2004-11-10

申请号：EP03705200.8

申请日：2003-02-14

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： OGAWA, Hisashi ,  NAKAOKA, Hiroaki ,  KAJIYA, Atsuhiro ,  HASHIMOTO, Shin ,  EGASHIRA, Kyoko

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/10

CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897

摘要： A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a , and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

摘要翻译： 存储单元晶体管和平面电容器被提供在存储区域中，并且CMOS器件的两个晶体管被提供在逻辑电路区域中。 平面电容器的电容电介质15和平板电极16b设置在与浅沟槽隔离12a共享的沟槽上方，并且沟槽的上部填充有电容电介质15和平板电极16b。 作为存储节点的n型扩散层19形成为其端部区域沿着沟槽的上部的一侧延伸到与浅沟槽隔离部12a重叠的衬底的区域。 用作电容器的基板的一部分的面积可以增加而不增加基板面积。

公开(公告)号：EP1475838A1

公开(公告)日：2004-11-10

申请号：EP03705199.2

申请日：2003-02-14

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： OGAWA, Hisashi ,  MIYANAGA, Isao ,  ERIGUCHI, Koji ,  YAMADA, Takayuki ,  ITONAGA, Kazuichiro ,  MORI, Yoshihiro

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/10

CPC分类号： H01L27/10882 ,  H01L27/10829 ,  H01L27/10894 ,  Y10S257/905 ,  Y10S257/908

摘要： A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30 . In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18 . A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32 .

摘要翻译： 存储器单元晶体管和沟槽电容器被提供在存储器区域中，并且CMOS的两个晶体管被提供在逻辑电路区域中。 提供了在层间电介质30上延伸的位线接触31和位线32.在存储单元晶体管中，源极扩散层18被存储单元晶体管中的两个电介质侧壁25a和25b覆盖， 硅化物层形成在源极扩散层18上。提供板触点31以穿过层间电介质30并将屏蔽线33连接到板电极16b。 屏蔽线33布置在与位线32相同的互连层中。

公开(公告)号：EP1359622A1

公开(公告)日：2003-11-05

申请号：EP01273090.9

申请日：2001-12-28

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： OGAWA, Hisashi ,  MORI, Yoshihiro ,  TSUZUMITANI, Akihiko

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10885 ,  H01L28/55 ,  H01L28/60 ,  Y10S257/905 ,  Y10S257/908

摘要： A memory cell in a DRAM, which is a semiconductor memory device, is provided with a bit line 21a connected to a bit line plug 20b and a local interconnect 21b , over a first interlevel insulating film 18 . A conductor sidewall 40 of TiAIN is formed on side faces of hard mask 37, upper barrier metal 36, Pt film 35 and BST film 34. No contact hole is provided on the Pt film 35 constituting an upper electrode 35a . The upper electrode 35a is connected to an upper interconnect (a Cu interconnect 42 ) via the conductor sidewall 40 , dummy lower electrode 33b , dummy cell plug 30 and local interconnect 21b . The Pt film 35 is not exposed to a reducing atmosphere, and therefore deterioration in characteristics of the capacitive insulating film 34a can be prevented.

摘要翻译： 作为半导体存储器件的DRAM中的存储单元在第一层间绝缘膜18上设置有连接到位线插头20b和局部互连21b的位线21a。形成TiAIN的导体侧壁40 在硬掩模37，上阻挡金属36，Pt膜35和BST膜34的侧面上。在构成上电极35a的Pt膜35上没有设置接触孔。 上电极35a经由导体侧壁40，虚拟下电极33b，虚设电池插塞30和局部互连21b连接到上互连（Cu互连42）。 Pt膜35没有暴露于还原气氛中，因此可以防止电容绝缘膜34a的特性劣化。