发明公开
EP1399858A2 HARDWARE-ASSISTED DESIGN VERIFICATION SYSTEM USING A PACKET-BASED PROTOCOL LOGIC SYNTHESIZED FOR EFFICIENT DATA LOADING AND UNLOADING
审中-公开
SYSTEM FOR硬件辅助设计审查使用逻辑合成基于分组的协议高效数据的加载和放电
- 专利标题： HARDWARE-ASSISTED DESIGN VERIFICATION SYSTEM USING A PACKET-BASED PROTOCOL LOGIC SYNTHESIZED FOR EFFICIENT DATA LOADING AND UNLOADING
- 专利标题（中）： SYSTEM FOR硬件辅助设计审查使用逻辑合成基于分组的协议高效数据的加载和放电
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申请号： EP01271071.1申请日： 2001-10-19
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公开(公告)号： EP1399858A2公开(公告)日： 2004-03-24
- 发明人: OHKAMI, Takahide
- 申请人： Quickturn Design Systems, Inc.
- 申请人地址： 2655 Seeley Avenue,Building 5 San Jose, California 95134 US
- 专利权人： Quickturn Design Systems, Inc.
- 当前专利权人： Quickturn Design Systems, Inc.
- 当前专利权人地址： 2655 Seeley Avenue,Building 5 San Jose, California 95134 US
- 代理机构： Viering, Jentschura & Partner
- 优先权： US242407P 20001020; US879658 20010611
- 国际公布： WO2002063507 20020815
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A system is prvided to increase the accessibility of registers and memories in a user's design undergoing functional verificationin a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and ahardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.
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