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    System and method for providing compact mapping between dissimilar memory systems
    2.
    发明公开
    System and method for providing compact mapping between dissimilar memory systems 审中-公开
    系统与Verfahren zur Bereitstellung von kompaktem Mapping zwischen ungleichen Speichersystemen

    公开(公告)号：EP1710722A1

    公开(公告)日：2006-10-11

    申请号：EP06007305.3

    申请日：2006-04-06

    申请人： QUICKTURN DESIGN SYSTEMS, INC. ,  Birguer, Alexandre

    发明人： Birguer, Alexandre

    IPC分类号： G06F17/50

    CPC分类号： G06F12/1072 ,  G06F17/5027

    摘要： A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system witbout a loss of memory space in the second memory system. Advantageously, the memory mapping system can be applied to hardware emulator memory systems to more efficiently map design memory systems into an emulation memory system during compilation.

    摘要翻译： 一种用于在不同的存储器系统之间提供紧凑映射的存储器映射系统以及用于制造和使用它们的方法。 存储器映射系统可以将内容从一个或多个第一存储器系统紧凑地映射到第二存储器系统中，同时存在第二存储器系统中的存储器空间的损失。 有利地，存储器映射系统可以应用于硬件仿真器存储器系统，以在编译期间将设计存储器系统更有效地映射到仿真存储器系统中。

    Method for stimulating functional logic circuit with logical stimulus
    3.
    发明公开
    Method for stimulating functional logic circuit with logical stimulus 失效
    刺激具有逻辑刺激的功能逻辑电路的方法

    公开(公告)号：EP1462964A2

    公开(公告)日：2004-09-29

    申请号：EP04008856.9

    申请日：1989-10-04

    申请人： QUICKTURN DESIGN SYSTEMS, INC.

    发明人： Butts, Michael R. ,  Batcheller, Jon A.

    IPC分类号： G06F17/50

    CPC分类号： G06F15/7867 ,  G06F17/5027 ,  G06F17/5054 ,  G06F17/5068

    摘要： A method is claimed for stimulating a functional circuit with logical stimulus, in order to determine the response of the functional circuit to that logical stimulus. The claimed method comprises the steps of (a) configuring a reconfigurable logic apparatus to implement the functional circuit, said reconfigurable logic apparatus comprising N reprogrammable logic devices, where N is a number greater than one, said N reprogrammable logic devices being interconnected by reprogrammable interconnect devices, and said functional circuit being implemented by at least two of said N reprogrammable logic devices; (b) converting the logical stimulus into input electrical signals; (c) inputting said electrical signals to said N reconfigurable logic apparatus which is configured with the functional circuit; and (d) receiving output electrical signals from said reconfigurable logic apparatus; and (e) converting said output electrical signals into software form.
    Also claimed are methods of simulating a functional circuit design, and a method of simulating digital logic networks.

    摘要翻译： 一种方法方面作了权利要求，以确定矿所述功能电路的逻辑刺激的反应没有刺激与逻辑刺激的功能电路中，为了。 所要求保护的方法，包括：（A）配置的可重新配置的逻辑设备来实现所述功能电路的步骤，所述可重新配置逻辑设备包括N个可重编程的逻辑器件，其中N是大于一的数，由可重编程互连互相连接，所述N个可再编程逻辑器件 设备，并且所述功能电路由至少两个所述的N可重编程逻辑器件的正在执行; （B）将所述逻辑输入激励转换成电信号; （C）输入所述电信号至所述n个可重新配置逻辑设备的所有其配置与功能电路; 和（d）接收来自可重构逻辑的所述设备的电输出信号; 和（e）将所述输出电信号转换成软件形式。因此，要求保护的是模拟的功能的电路设计的方法，以及模拟数字逻辑网络的方法。

    Method and apparatus for design verification using emulation and simulation
    4.
    发明公开
    Method and apparatus for design verification using emulation and simulation 失效
    方法和装置的设计的验证使用仿真和模拟

    公开(公告)号：EP0838772A2

    公开(公告)日：1998-04-29

    申请号：EP97117782.9

    申请日：1997-10-14

    申请人： QUICKTURN DESIGN SYSTEMS, INC.

    发明人： Sample, Stephen P. ,  Bershteyn, Mikhail

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5027

    摘要： A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

    摘要翻译： 一种用于组合逻辑设计的仿真和模拟方法和装置。 该方法和装置可以与逻辑设计中使用没有包括门级描述，行为的表示，结构表示，或它们的组合。 仿真和模拟部分以这样的方式被组合做最小化在两个部分之间传递环数据的时间。 如现场可编程门阵列：模拟由一个或多个微处理器，而仿真执行在重新配置的硬件来执行。 当多个微处理器采用，被选择的逻辑设计的独立部分上的所述多个同步的微处理器执行。 因此，可重构硬件执行事件检测和调度操作，以帮助仿真，并减少处理时间。

    Method, apparatus and computer-readable medium for simulation and visualization data transfer between an emulation system and a simulator
    6.
    发明公开
    Method, apparatus and computer-readable medium for simulation and visualization data transfer between an emulation system and a simulator 审中-公开
    的方法，设备和计算机可读介质用于仿真系统和模拟器之间的数据传输的模拟和可视

    公开(公告)号：EP1533723A2

    公开(公告)日：2005-05-25

    申请号：EP04027295.7

    申请日：2004-11-17

    申请人： Quickturn Design Systems, Inc.

    发明人： Quayle, Barton ,  Poplack, Mitchell G.

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5027 ,  G06F17/5022 ,  G06F2217/86

    摘要： An optimized interface (20) for simulation and visualization data transfer between an emulation system (30) and a simulator (10) is disclosed. In one embodiment, a method of transferring data between the simulator and the emulator across the interface comprises updating (605) a simulator buffer (18) of the simulator to contain a desired input state for an emulation cycle. A target write (610) to the interface is performed to indicate that the emulation cycle can proceed. The emulation cycle (615, 620, 625, 630) is completed using an instruction sequencer (50) within the interface independent of the simulator.

    摘要翻译： 在仿真系统（30）之间模拟和可视数据传输和模拟器（10）一种优化的接口（20）是圆盘游离缺失。 在一个，实施例中，模拟器和跨越接口仿真器之间传递环数据的方法包括更新（605）所述模拟器的模拟器缓冲液（18）以包含所希望的输入状态为在仿真周期。 靶写入（610）到接口被执行以指示DASS模具仿真循环可以继续进行。 仿真周期（615，620，625，630）是使用对接口独立模拟器的内指令定序器（50）完成。

    Method and apparatus for design verification using emulation and simulation
    9.
    发明公开
    Method and apparatus for design verification using emulation and simulation 失效
    使用仿真和仿真进行设计验证的方法和设备

    公开(公告)号：EP0838772A3

    公开(公告)日：1998-05-13

    申请号：EP97117782.9

    申请日：1997-10-14

    申请人： QUICKTURN DESIGN SYSTEMS, INC.

    发明人： Sample, Stephen P. ,  Bershteyn, Mikhail

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5027

    摘要： A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

    摘要翻译： 一种用于组合逻辑设计的仿真和仿真的方法和设备。 该方法和装置可以与包括门级描述，行为表示，结构表示或其组合的逻辑设计一起使用。 仿真部分和仿真部分以最小化两部分之间传输数据的时间的方式组合。 仿真由一个或多个微处理器执行，而仿真在可重新配置的硬件（如现场可编程门阵列）中执行。 当采用多个微处理器时，逻辑设计的独立部分被选择为在多个同步微处理器上执行。 可重新配置的硬件还执行事件检测和调度操作以帮助模拟，并减少处理时间。