A ferroelectric three-dimensional solid-state memory is formed from a plurality of bit lines, a plurality of layers, a plurality of tree structures and a plurality of plate lines. The bit lines are arranged in a first plane and extend in a first direction. Each layer includes an array of ferroelectric capacitor memory cells. Each tree structure corresponds to a bit line and has a trunk portion and a plurality of branch portions. The trunk portion of each tree structure extends from a corresponding bit line. Each branch portion corresponds to a layer and extends from the trunk portion of the tree structure. Plate lines is arranged in each layer and overlap the branch portion of each tree structure in the corresponding layer at a plurality of intersection regions. A 0T-FeRAM memory cell is located at each intersection region in a layer.