公开(公告)号：EP1615205A1

公开(公告)日：2006-01-11

申请号：EP05103702.6

申请日：2005-05-03

申请人： Hitachi Global Storage Technologies B. V.

发明人： Stipe, Barry Cushing ,  Thiele, Jan-Ulrich

IPC分类号： G11B5/73 ,  G11B5/64

CPC分类号： G11B5/667 ,  G11B5/012 ,  G11B5/1278 ,  G11B5/65 ,  G11B5/7325 ,  G11B5/743 ,  G11B5/82 ,  G11B5/84

摘要： A recording medium according to the invention has a magnetic recording layer with an L1 0 magnetic material deposited with a (111) preferred orientation and soft underlayer (SUL). One set of embodiments includes an intermediate layer (seed layer or underlayer) between the L1 0 media and SUL. The intermediate layer can be a close-packed surface structure (triangular lattice) to promote (111) orientation of the L1 0 media. For example, the intermediate layer can be a (111) oriented, face-centered-cubic (fcc) material such as platinum, palladium, iridium, rhodium, FePt, FePd, or FePdPt alloys; or the intermediate layer can be a (100) oriented hexagonal-close-packed (hcp) material such as ruthenium, rhenium, or osmium. Alternatively, the intermediate layer can be an amorphous material. The L1 0 recording layer of the invention can be deposited with a matrix material to form grain boundaries and provide magnetic isolation of the grains of L1 0 material.

摘要翻译： 根据本发明的记录介质具有磁记录层，其具有沉积有（111）优选取向和软底层（SUL）的L1 0磁性材料。 一组实施例包括L1 0介质和SUL之间的中间层（种子层或底层）。 中间层可以是紧密堆积的表面结构（三角形晶格）以促进L1 0介质的（111）取向。 例如，中间层可以是（111）取向的面心立方（fcc）材料，例如铂，钯，铱，铑，FePt，FePd或FePdPt合金; 或中间层可以是（100）取向的六方密堆积（hcp）材料，例如钌，铼或锇。 或者，中间层可以是无定形材料。 本发明的L1 0记录层可以用基质材料沉积以形成晶界并提供L1 0材料的晶粒的磁隔离。

公开(公告)号：EP1492124A3

公开(公告)日：2005-10-26

申请号：EP04010382.2

申请日：2004-04-30

申请人： Hitachi Global Storage Technologies B. V.

发明人： Stipe, Barry Cushing

IPC分类号： G11C11/22 ,  H01L27/10

CPC分类号： H01L27/11507 ,  G11C7/18 ,  G11C11/22 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/82 ,  H01L27/11502 ,  H01L27/24

摘要： A ferroelectric three-dimensional solid-state memory is formed from a plurality of bit lines, a plurality of layers, a plurality of tree structures and a plurality of plate lines. The bit lines are arranged in a first plane and extend in a first direction. Each layer includes an array of ferroelectric capacitor memory cells. Each tree structure corresponds to a bit line and has a trunk portion and a plurality of branch portions. The trunk portion of each tree structure extends from a corresponding bit line. Each branch portion corresponds to a layer and extends from the trunk portion of the tree structure. Plate lines is arranged in each layer and overlap the branch portion of each tree structure in the corresponding layer at a plurality of intersection regions. A 0T-FeRAM memory cell is located at each intersection region in a layer.

公开(公告)号：EP1615205B1

公开(公告)日：2008-12-03

申请号：EP05103702.6

申请日：2005-05-03

申请人： Hitachi Global Storage Technologies B. V.

发明人： Stipe, Barry Cushing ,  Thiele, Jan-Ulrich

IPC分类号： G11B5/73 ,  G11B5/64

CPC分类号： G11B5/667 ,  G11B5/012 ,  G11B5/1278 ,  G11B5/65 ,  G11B5/7325 ,  G11B5/743 ,  G11B5/82 ,  G11B5/84

公开(公告)号：EP1492124A2

公开(公告)日：2004-12-29

申请号：EP04010382.2

申请日：2004-04-30

申请人： Hitachi Global Storage Technologies B. V.

发明人： Stipe, Barry Cushing

IPC分类号： G11C11/22

CPC分类号： H01L27/11507 ,  G11C7/18 ,  G11C11/22 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/82 ,  H01L27/11502 ,  H01L27/24

摘要： A ferroelectric three-dimensional solid-state memory is formed from a plurality of bit lines, a plurality of layers, a plurality of tree structures and a plurality of plate lines. The bit lines are arranged in a first plane and extend in a first direction. Each layer includes an array of ferroelectric capacitor memory cells. Each tree structure corresponds to a bit line and has a trunk portion and a plurality of branch portions. The trunk portion of each tree structure extends from a corresponding bit line. Each branch portion corresponds to a layer and extends from the trunk portion of the tree structure. Plate lines is arranged in each layer and overlap the branch portion of each tree structure in the corresponding layer at a plurality of intersection regions. A 0T-FeRAM memory cell is located at each intersection region in a layer.

摘要翻译： 该装置具有多个树（302），每个树对应于形成在基板上的每个位线，并且具有中继线（305）和多个分支（306）。 从中继线延伸的每个分支对应于具有存储单元阵列的多个层之一。 具有多个板条（307）的多个板状线组中的每一个在存储单元（301）所在的许多交叉区域与每棵树的分支重叠。 还包括以下独立权利要求：（1）读取和擦除存储器件的方法; 和（2）将数据写入先前擦除的存储器件的方法。