A duobinary-to-binary signal converter includes a pair of comparators coupled to a logic gate. Each comparator receives a copy of a duobinary-encoded analog signal applied to the converter and is designed to generate a binary output based on the comparison of the magnitude of the received signal with a corresponding threshold voltage. The outputs of the comparators are fed into the logic gate, which generates a binary sequence corresponding to the duobinary-encoded signal. A representative converter of the invention can perform relatively well at bit rates as high as about 40 Gb/s and can be conveniently incorporated into an appropriate integrated device (e.g., an ASIC) for a data transmission system employing duobinary signaling.