发明公开
- 专利标题： SUBLITHOGRAPHIC NANOSCALE MEMORY ARCHITECTURE
- 专利标题（中）： 次光刻NANO区存储器架构
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申请号： EP03796282.6申请日： 2003-07-24
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公开(公告)号： EP1525586A2公开(公告)日： 2005-04-27
- 发明人: DEHON, Andre , LIEBER, Charles, M. , LINCOLN, Patrick, D. , SAVAGE, John
- 申请人： California Institute of Technology , PRESIDENT AND FELLOWS OF HARVARD COLLEGE , Sri International , Brown University
- 申请人地址： 1200 East California Boulevard,Mail Code 201-85 Pasadena, CA 91125 US
- 专利权人： California Institute of Technology,PRESIDENT AND FELLOWS OF HARVARD COLLEGE,Sri International,Brown University
- 当前专利权人： California Institute of Technology,PRESIDENT AND FELLOWS OF HARVARD COLLEGE,Sri International,Brown University
- 当前专利权人地址： 1200 East California Boulevard,Mail Code 201-85 Pasadena, CA 91125 US
- 代理机构： Ebner von Eschenbach, Jennifer
- 优先权： US398943P 20020725; US400394P 20020801; US415176P 20020930; US429010P 20021125; US441995P 20030123; US465357P 20030425; US467388P 20030502
- 国际公布： WO2004034467 20040422
- 主分类号： G11C13/02
- IPC分类号： G11C13/02
摘要：
A memory array comprising nanoscale wires (61-72) is disclosed. The nanoscale wiresare addressed by means of controllable regions (80, 82) axially and/or radiallydistributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires andmicroscale wires. In a two-dimensional emobdiment, memory locations (75) aredefined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing pointsbetween nanoscale wires located in different vertical layers.
公开/授权文献
- EP1525586B1 SUBLITHOGRAPHIC NANOSCALE MEMORY ARCHITECTURE 公开/授权日：2007-04-25
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