Typically, a bulk of the memory space utilized by an SOC (103) is located in cheaper off-chip memory devices such as Synchronous Dynamic Random Access Memory (SDRAM) memories (104). These memories provide a large capacity for data storage, at a relatively low cost. It is common for SOC devices to communicate with each other through these off-chip memory devices. Because of the large amount of data being processed on state of the art SOCs, the data bandwidth to and from the SDRAM memories is a critical resource, which if improperly managed results in bottlenecks. Thus, a novel address mapping scheme, which has improved efficiency for two-dimensional memory transactions is proposed for mapping on-chip memory transactions to off-chip memory transactions. This novel mapping scheme aims to decrease these bottlenecks, by segmenting the data sequence into portions being smaller than the size of a row of a block of the SDRAM memories.