公开(公告)号：EP2568658A2

公开(公告)日：2013-03-13

申请号：EP12178622.2

申请日：2012-07-31

申请人： NXP B.V. ,  NXP B.V.

发明人： Shrestha, Rameswor ,  Smeets, Patrick Emanuel Gerardus

IPC分类号： H04L12/12

CPC分类号： H04B5/0012 ,  H04B5/0031 ,  H04L25/0268

摘要： Data is communicated. In accordance with one or more example embodiments, a communications circuit communicates a digital data signal using a carrier signal having a frequency that is different than the frequency of the data signal. The communications circuit includes first and second sets of capacitors, a first circuit and a second circuit. The first circuit generates mixed data signals respectively mixed with the carrier signal and an inverse of the carrier signal, generates mixed inverted data signals respectively mixed with the carrier signal and an inverse of the carrier signal, provides the mixed data signals to the first set of capacitors, and provides the mixed inverted data signals to the second set of capacitors. The second circuit recovers the data signal from the mixed signals.

摘要翻译： 数据传达。 根据一个或多个示例实施例，通信电路使用具有与数据信号的频率不同的频率的载波信号来传送数字数据信号。 通信电路包括第一和第二组电容器，第一电路和第二电路。 第一电路产生分别与载波信号和载波信号的反相混合的混合数据信号，产生分别与载波信号和载波信号的反相混合的混合反相数据信号，将混合数据信号提供给第一组 电容器，并将混合的反相数据信号提供给第二组电容器。 第二个电路从混合信号中恢复数据信号。

公开(公告)号：EP4095753B1

公开(公告)日：2024-10-30

申请号：EP22173390.0

申请日：2022-05-13

发明人： PICHLER, Thomas ,  REBOLLO PIMENTEL, Ivan Jesus

IPC分类号： G06K19/07 ,  H02M3/07 ,  H02M1/08

公开(公告)号：EP4443498A1

公开(公告)日：2024-10-09

申请号：EP24167596.6

申请日：2024-03-28

申请人： NXP B.V.

发明人： CHUANG, Wen Yuan ,  MAO, Kuan-Hsiang ,  HUANG, Wen Hung

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495

CPC分类号： H01L21/486 ,  H01L23/5389 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/82 ,  H01L24/16 ,  H01L23/49548 ,  H01L23/49541 ,  H01L23/49582 ,  H01L21/6835 ,  H01L2221/6833120130101 ,  H01L2221/6834520130101 ,  H01L21/561

摘要： A leadless semiconductor package includes an integrated circuit (IC) die having one or more contacts at an active surface facing a mounting surface of the leadless semiconductor package. The leadless semiconductor package further includes a plurality of dual-sided stud structures providing electrical connectivity between the IC die and the mounting surface, each dual-sided stud structure having at least one first conductive pillar structure extending from a corresponding contact at the active surface to a redistribution layer and having at least one second conductive pillar structure extending from a redistribution layer to an edge of the mounting surface, each first conductive pillar structure having a first dimension in a direction parallel to the mounting surface that is less than a corresponding second dimension of each second conductive pillar structure. Solder wettable flanks may be formed at the external sidewall edges of the second conductive pillar structures to facilitate soldering or inspection.

公开(公告)号：EP4443266A1

公开(公告)日：2024-10-09

申请号：EP24167628.7

申请日：2024-03-28

申请人： NXP B.V.

发明人： Lee, Jang Hyuck ,  Lee, Jin Hui

IPC分类号： G05F3/26 ,  H02M1/00

CPC分类号： G05F3/26 ,  H02M1/0003

摘要： A current leakage limit circuit connected to a circuit with current leakage and a leakage compensation circuit includes a first current mirror with a first transistor and a second transistor and a current source connected to the first transistor. The second transistor is connected between the circuit and the leakage compensation circuit and limits a compensation current flowing between the circuit and the leakage compensation circuit. The current flowing from the current source through the first transistor limits the current flowing through the second transistor.

公开(公告)号：EP3848918B1

公开(公告)日：2024-10-02

申请号：EP20150803.3

申请日：2020-01-08

IPC分类号： G08C17/02

CPC分类号： G08C17/02 ,  G08C2201/7020130101

公开(公告)号：EP4432607A1

公开(公告)日：2024-09-18

申请号：EP24161988.1

申请日：2024-03-07

申请人： NXP B.V.

发明人： van Vredendaal, Christine ,  Fay, Björn ,  Lamberger, Mario

IPC分类号： H04L9/40 ,  H04W12/30 ,  H04L9/08

CPC分类号： H04L63/062 ,  H04W12/35 ,  H04L9/0852 ,  H04L9/50 ,  H04L9/0897

摘要： A method for provisioning a plurality of IC devices, the method including: providing, by a first entity, the plurality of IC devices; storing, by the first entity, in one of the plurality of IC devices used as a provisioning device, one or more keys, and a public key, wherein the one or more keys include a reprovisioning key for reprovisioning the remaining IC devices; installing, by the first entity, provisioning software in the provisioning device; signing, by the first entity, provisioning software using a private key, the private key corresponding to the public key; provisioning the remaining IC devices by the provisioning device including providing cryptographic assets to the remaining IC devices, wherein the cryptographic assets include cryptographic code and keys; and reserving space in the remaining IC devices for reprovisioning the remaining IC devices with updated cryptographic assets.

公开(公告)号：EP4432140A1

公开(公告)日：2024-09-18

申请号：EP23161539.4

申请日：2023-03-13

申请人： NXP B.V.

发明人： Lehment, Nicolas Harmen ,  Michiels, Wilhelmus Petrus Adrianus Johannus

IPC分类号： G06F21/16 ,  G06N3/00

CPC分类号： G06F21/16 ,  H04L2209/60820130101 ,  G06N3/063 ,  H04L9/3247

摘要： In accordance with a first aspect of the present disclosure, a hardware accelerator is provided, comprising: an execution unit configured to execute at least one artificial intelligence (AI) model using one or more resources of the hardware accelerator; a watermark verification unit configured to verify whether a predefined watermark is present in the AI model and to output a verification result indicative of the presence or absence of said watermark; a resource management unit configured to enable said resources if the verification result indicates that the watermark is present. Further aspects of the present disclosure relate to a corresponding method of operating a hardware accelerator, and to a computer program for carrying out said method.

公开(公告)号：EP4432098A1

公开(公告)日：2024-09-18

申请号：EP23162054.3

申请日：2023-03-15

申请人： NXP B.V.

发明人： Costa, Raffaele ,  Castelnuovo, Andrea ,  Deloge, Matthieu ,  Storms, Maurits Mario Nicolaas ,  Masferrer Oncala, Sergio

IPC分类号： G06F12/02 ,  G11C29/00 ,  G11C29/44

CPC分类号： G06F12/0238 ,  G06F2212/720120130101 ,  G06F2212/720420130101 ,  G06F2212/104420130101 ,  G06F2212/720220130101 ,  G06F2212/721120130101 ,  G06F2212/103620130101 ,  G11C29/4401 ,  G11C29/883

摘要： Disclosed is a method of storing data in a stuck-cell memory page of a memory array, the stuck-cell memory page having a cell at a stuck-cell-identifier cell of the memory page stuck at a stuck-cell-value, the method comprising: identifying a match between a first dataset and the stuck-cell memory page; and storing the dataset in the stuck-cell memory page; wherein the identifying a match comprises identifying that the at least one bit of the dataset which corresponds to the stuck-cell-identifier of the memory cell has a value which is equal to the stuck-cell value. A memory system configured for the above method is further disclosed

公开(公告)号：EP4429117A1

公开(公告)日：2024-09-11

申请号：EP24153653.1

申请日：2024-01-24

申请人： NXP B.V.

发明人： Olieman, Erik ,  Litjes, Alphons ,  Van Veldhoven, Robert

IPC分类号： H03M1/06 ,  H03M1/12 ,  H03M1/46

CPC分类号： H03M1/0626 ,  H03M1/0692 ,  H03M1/0697 ,  H03M1/12 ,  H03M1/462

摘要： A system and method of analog to digital conversion including an adjustable ADC, FIR filter circuitry, and a noise setting controller. The ADC samples an analog input signal to provide digital samples at a sample rate that is Y times an output rate of output digital values. The FIR filter circuitry includes Y taps with Y corresponding coefficients and is configured to filter the digital samples from the ADC and to provide filtered digital samples at the sample rate. decimation circuitry may be included to decimate the filtered digital samples by Y to provide the output digital values. The noise setting controller provides an adjustment value to the ADC to adjust noise contribution of the digital samples provided by the ADC based on corresponding coefficients of the FIR filter circuitry. The ADC is adjusted to reduce noise contribution of digital samples that correspond with higher FIR filter coefficients.

公开(公告)号：EP4428923A1

公开(公告)日：2024-09-11

申请号：EP23160685.6

申请日：2023-03-08

申请人： NXP B.V.

发明人： Donkers, Johannes Josephus Theodorus Marinus ,  John, Jay Paul ,  Kirchgessner, James Albert ,  Sebel, Patrick

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/737

CPC分类号： H01L29/7371 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/0649

摘要： Disclosed is a SiGe heterojunction bipolar transistor, HBT, and method of manufacturing the same, comprising: an n-doped buried collector (HV); a p-doped epitaxial monocrystalline SiGe base layer, within a layer stack, the layer stack (110) being over and in direct contact with the collector (HV); an n-doped monocrystalline silicon emitter (142) over a first area of the layer stack (110), the emitter provided with a polycrystalline silicon emitter contact layer (144) thereon; an epitaxial silicon base contact layer (218) over a second area of the layer stack (110); an oxide layer (216) over a third area of the layer stack between the first and second areas, wherein the oxide layer (216) and the n-doped monocrystalline silicon emitter (142) are within a window in the epitaxial silicon base contact layer (218), the window having sidewalls; dielectric spacers (132) on the sidewalls of the window and over the oxide layer (216), and providing electrical isolation between the epitaxial silicon layer (218) and the polycrystalline silicon layer (144); the epitaxial silicon layer (218) extending beneath the dielectric spacers (132) on the sidewalls of the window and extending upward (218d) between the dielectric spacers (132) and a further dielectric layer (120).