An integrated circuit 1 comprises a timing closure monitoring circuit 2. The timing closure monitoring circuit 2 comprises a duplicate path 19, having the same characteristics as a logic path 3 being monitored. The duplicate path 19 receives a pulsed reference signal 23 from a reference generating unit (RGU) 24. The pulsed reference signal 23 is synchronized with the clock signal 13, and passed through the duplicate path 19 to a reference checking unit (RCU) 25. In a normal mode of operation in which timing closure is guaranteed, the clock signal 13 will sample the pulsed reference signal 23, such that no interrupt signal is generated on the interrupt line 33. However, in the situation where the reference check unit 25 is clocked by the clock signal 13 prior to the pulsed reference signal 23 being received via the duplicate path 19, an interrupt signal is generated on the interrupt line 33, indicating that timing closure cannot be guaranteed.