发明授权
EP1644823B1 LOAD STORE UNIT WITH REPLAY MECHANISM 有权
带有重复机制负载存储单元

LOAD STORE UNIT WITH REPLAY MECHANISM
摘要:
A microprocessor (100) may include a scheduler (118) configured to issue operations and a load store unit (126C) configured to execute memory operations issued by the scheduler (118). The load store unit (126C) is configured to store information identifying memory operations issued to the load store unit (126C). In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit (126C) is configured to replay at least one of the issued memory operations by providing an indication to the scheduler (118). The scheduler (118) is configured to responsively reissue the memory operations identified by the load store unit (126C).
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