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1.发明公开
公开(公告)号：EP1532521A2
公开(公告)日：2005-05-25
申请号：EP03791590.7
申请日：2003-07-16
IPC分类号： G06F9/38
CPC分类号： G06F9/3842
摘要： A microprocessor (100) may include several execution units (124) and a scheduler (118) coupled to issue operations to at least one of the execution units (124). The scheduler (118) may include several entries (320). A first entry may be allocated to a first operation. The first entry includes a source status indication (330A, 330B) for each of the first operation's operands. Each source status indication (330A, 330B) indicates whether a value of a respective one of the first operation's operands is speculative. The scheduler (118) is configured to update one of the first entry's source status indications (330A, 330B) to indicate that a value of a respective one of the first operation's operands is non-speculative in response to receiving an indication that a value of a result of a second operation is non-speculative.
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2.发明授权
公开(公告)号：EP1532521B1
公开(公告)日：2014-03-12
申请号：EP03791590.7
申请日：2003-07-16
IPC分类号： G06F9/38
CPC分类号： G06F9/3842
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公开(公告)号：EP2476060A1
公开(公告)日：2012-07-18
申请号：EP10755043.6
申请日：2010-09-09
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0815 , G06F2212/6026
摘要： A system and method for efficient data prefetching. A data stream stored in lower-level memory comprises a contiguous block of data used in a computer program. A prefetch unit in a processor detects a data stream by identifying a sequence of storage accesses referencing a contiguous blocks of data in a monotonically increasing or decreasing manner. After a predetermined training period for a given data stream, the prefetch unit prefetches a portion of the given data stream from memory without write permission, in response to an access that does not request write permission. Also, after the training period, the prefetch unit prefetches a portion of the given data stream from lower-level memory with write permission, in response to determining there has been a prior access to the given data stream that requests write permission subsequent to a number of cache misses reaching a predetermined threshold.
摘要翻译： 一种用于高效数据预取的系统和方法。 存储在较低级存储器中的数据流包括在计算机程序中使用的连续数据块。 处理器中的预取单元通过以单调递增或递减方式识别引用连续数据块的存储访问序列来检测数据流。 在给定数据流的预定训练周期之后，预取单元响应于不请求写入许可的访问，在没有写入许可的情况下从存储器中预取一部分给定数据流。 另外，在训练周期之后，预取单元响应于确定先前存在请求写入许可的给定数据流的先前访问权，从具有写许可的较低级存储器中预取一部分给定数据流 的高速缓存未命中达到预定阈值。
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公开(公告)号：EP1388065A2
公开(公告)日：2004-02-11
申请号：EP02717694.0
申请日：2002-03-21
IPC分类号： G06F12/08
CPC分类号： G06F12/0891
摘要： A cache controller (419) configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.
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公开(公告)号：EP2476060B1
公开(公告)日：2015-06-17
申请号：EP10755043.6
申请日：2010-09-09
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0815 , G06F2212/6026
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公开(公告)号：EP1644823B1
公开(公告)日：2007-11-21
申请号：EP04753838.4
申请日：2004-06-02
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3826 , G06F9/3832 , G06F9/3834 , G06F9/3861
摘要： A microprocessor (100) may include a scheduler (118) configured to issue operations and a load store unit (126C) configured to execute memory operations issued by the scheduler (118). The load store unit (126C) is configured to store information identifying memory operations issued to the load store unit (126C). In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit (126C) is configured to replay at least one of the issued memory operations by providing an indication to the scheduler (118). The scheduler (118) is configured to responsively reissue the memory operations identified by the load store unit (126C).
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公开(公告)号：EP1388065B1
公开(公告)日：2007-09-12
申请号：EP02717694.0
申请日：2002-03-21
IPC分类号： G06F12/08
CPC分类号： G06F12/0891
摘要： A cache controller (419) configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.
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公开(公告)号：EP1644823A1
公开(公告)日：2006-04-12
申请号：EP04753838.4
申请日：2004-06-02
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3826 , G06F9/3832 , G06F9/3834 , G06F9/3861
摘要： A microprocessor (100) may include a scheduler (118) configured to issue operations and a load store unit (126C) configured to execute memory operations issued by the scheduler (118). The load store unit (126C) is configured to store information identifying memory operations issued to the load store unit (126C). In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit (126C) is configured to replay at least one of the issued memory operations by providing an indication to the scheduler (118). The scheduler (118) is configured to responsively reissue the memory operations identified by the load store unit (126C).
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