发明公开
EP1742266A3 Semiconductor integrated circuit device, circuit design apparatus, and circuit design method
审中-公开
用于设计电路装置的半导体集成电路装置中，装置和方法
- 专利标题： Semiconductor integrated circuit device, circuit design apparatus, and circuit design method
- 专利标题（中）： 用于设计电路装置的半导体集成电路装置中，装置和方法
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申请号： EP06019712.6申请日： 2001-07-27
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公开(公告)号： EP1742266A3公开(公告)日： 2013-05-22
- 发明人: Suzuki, Kenji Fujitsu Limited , Tajima, Shogo Fujitsu Limited
- 申请人： Fujitsu Semiconductor Limited
- 申请人地址： 2-10-23 Shin-Yokohama Kohoku-ku, Yokohama-shi Kanagawa 222-0033 JP
- 专利权人： Fujitsu Semiconductor Limited
- 当前专利权人： Fujitsu Semiconductor Limited
- 当前专利权人地址： 2-10-23 Shin-Yokohama Kohoku-ku, Yokohama-shi Kanagawa 222-0033 JP
- 代理机构： Schultes, Stephan
- 优先权： JP2000396420 20001227
- 主分类号： H01L23/522
- IPC分类号： H01L23/522 ; G06F17/50 ; H01L21/768
摘要：
A semiconductor integrated circuit device in which wirings in different layers are connected electrically by vias and in which wiring width at a connection terminal is limited to the maximum width. A plurality of vias are arranged annularly in an area where a wiring in a lower layer and a wiring in an upper layer overlap. A pillar is generated in an area surrounded by the plurality of vias. Locating the pillar will narrow wiring width at a connection terminal for making interlayer connection. Furthermore, the plurality of vias arranged around the pillar will ensure a good connection.
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