公开(公告)号：EP2302663B1

公开(公告)日：2019-05-01

申请号：EP11150568.1

申请日：2006-01-23

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi

IPC: H01L21/02 ,  H01L23/522 ,  H01L49/02

公开(公告)号：EP1730628B1

公开(公告)日：2018-12-26

申请号：EP05729094.2

申请日：2005-03-30

Applicant: Fujitsu Semiconductor Limited ,  Synopsys, Inc.

Inventor： LIPPETT, Mark David

IPC: G06F9/38 ,  G06F15/80 ,  G06F15/78

CPC classification number: G06F9/3885 ,  G06F9/3851 ,  G06F9/3891

Abstract: A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters.

公开(公告)号：EP1679743B1

公开(公告)日：2018-10-10

申请号：EP05011032.9

申请日：2005-05-20

Applicant: Fujitsu Semiconductor Limited

Inventor： Hatada, Akiyoshi ,  Katakami, Akira ,  Tamura, Naoyoshi ,  Shimamune, Yosuke ,  Shima, Masashi ,  Ohta, Hiroyuki

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S438/933

Abstract: A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor includes a first gate electrode carrying a pair of first sidewall insulation films formed on respective sidewall surfaces thereof, the p-channel MOS transistor includes a second gate electrode carrying a pair of second sidewall insulation films formed on respective sidewall surfaces thereof, first and second SiGe mixed crystal regions being formed in the second device region epitaxially so as to fill first and second trenches formed at respective, outer sides of the second sidewall insulation films so as to be included in source and drain diffusions of the p-channel MOS transistor, a distance between n-type source and drain diffusion region in the first device region being larger than a distance between the p-type source and drain diffusion regions in the second device region.

公开(公告)号：EP1612861B1

公开(公告)日：2018-10-03

申请号：EP03816642.7

申请日：2003-04-10

Applicant: Fujitsu Semiconductor Limited

Inventor： EMA, Taiji, c/o FUJITSU LIMITED ,  KOJIMA, Hideyuki, c/o FUJITSU LIMITED ,  ANEZAKI, Toru, c/o FUJITSU LIMITED

IPC: H01L27/088

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892

Abstract: Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.

公开(公告)号：EP2894669B1

公开(公告)日：2018-04-18

申请号：EP14200554.5

申请日：2014-12-30

Applicant: Fujitsu Semiconductor Limited

Inventor： Saito, Hitoshi

IPC: H01L27/08 ,  H01L49/02 ,  H01L27/108 ,  H01L27/115

CPC classification number: H01L27/11502 ,  H01L27/0805 ,  H01L27/108 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/56 ,  H01L28/60

Abstract: An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.

公开(公告)号：EP1693897B1

公开(公告)日：2018-03-07

申请号：EP05010736.6

申请日：2005-05-18

Applicant: Fujitsu Semiconductor Limited

Inventor： Tamura, Naoyoshi ,  Shimamune, Yosuke ,  Hatada, Akiyoshi ,  Katakami, Akira ,  Shima, Masashi

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/165 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/165 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate in correspondence to a channel region via a gate insulation film, and source and drain regions of p-type formed in the silicon substrate at respective outer sides of sidewall insulation films on the gate electrode, a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films epitaxially to the silicon substrate so as to be enclosed respectively by the source and drain regions, each of the SiGe mixed crystal regions being grown to a level above a level of a gate insulation film interface between the gate insulation film and the silicon substrate, wherein there is provided a compressive stress film at respective top surfaces of the SiGe mixed crystal regions.

公开(公告)号：EP2648220B1

公开(公告)日：2017-11-08

申请号：EP13175277.6

申请日：2006-06-30

Applicant: Fujitsu Semiconductor Limited

Inventor： EmaMA, Taiji ,  Mizutani, Kazuhiro

IPC: H01L27/11526 ,  H01L21/762 ,  H01L27/11536 ,  H01L27/11548

CPC classification number: H01L29/788 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/42336 ,  H01L29/7881

公开(公告)号：EP1619720B1

公开(公告)日：2017-02-22

申请号：EP04027491.2

申请日：2004-11-19

Applicant: Fujitsu Semiconductor Limited

Inventor： Anezaki, Toru ,  Tsutsumi, Tomohiko ,  Araya, Tatsuji ,  Kojima, Hideyuki ,  Ema, Taiji

IPC: H01L27/11 ,  H01L21/8244

CPC classification number: H01L27/1104 ,  G11C5/063 ,  G11C11/412 ,  H01L27/11 ,  Y10S257/903

公开(公告)号：EP0977259B1

公开(公告)日：2017-02-22

申请号：EP99305145.7

申请日：1999-06-30

Applicant: Fujitsu Semiconductor Limited

Inventor： Ooyama, Nobuo ,  Maki, Shinichiro ,  Fujisaki, Fumitoshi ,  Kuramoto, Syunichi ,  Saigo, Yukio ,  Yatsuda, Yasuo ,  Matae, Youichi ,  Yano, Atsushi ,  Tetaka, Masafumi ,  Tsuji, Kazuto

IPC: H01L23/31

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/85001 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H05K3/20 ,  H05K3/4007 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

公开(公告)号：EP1805621B1

公开(公告)日：2016-08-17

申请号：EP05779159.2

申请日：2005-09-13

Applicant: Synopsys, Inc. ,  Fujitsu Semiconductor Limited

Inventor： LIPPETT, Mark, David ,  OUNG, Ayewin

IPC: G06F11/36

CPC classification number: G06F11/3636