发明公开
EP1814234A2 Concurrent code checker and hardware efficient high- speed I/O having built- in self- test and debug features
有权
同时代码审计和硬件高效的输入/输出以高速与内建自测试和调试功能
- 专利标题： Concurrent code checker and hardware efficient high- speed I/O having built- in self- test and debug features
- 专利标题（中）： 同时代码审计和硬件高效的输入/输出以高速与内建自测试和调试功能
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申请号： EP07250229.7申请日： 2007-01-19
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公开(公告)号： EP1814234A2公开(公告)日： 2007-08-01
- 发明人: Sul, Chinsong , Choi, Hoon , Ahn, Gijung
- 申请人： Silicon Image, Inc.
- 申请人地址： 1060 East Arques Avenue Sunnyvale, California 94085 US
- 专利权人： Silicon Image, Inc.
- 当前专利权人： Silicon Image, Inc.
- 当前专利权人地址： 1060 East Arques Avenue Sunnyvale, California 94085 US
- 代理机构： Hackney, Nigel John
- 优先权： US760601P 20060120; US476457 20060627
- 主分类号： H03M13/21
- IPC分类号： H03M13/21 ; H03M13/33 ; H03M13/09
摘要：
Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.
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