发明公开
EP1872407A2 USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES
有权
金属/金属氮化物双层AS栅极电极的自对准AGGRESSIVE缩放CMOS组件使用
- 专利标题： USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES
- 专利标题（中）： 金属/金属氮化物双层AS栅极电极的自对准AGGRESSIVE缩放CMOS组件使用
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申请号： EP06750529.7申请日： 2006-04-18
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公开(公告)号： EP1872407A2公开(公告)日： 2008-01-02
- 发明人: CARTIER, Eduard, A. , COPEL, Matthew, W. , DORIS, Bruce, B. , JAMMY, Rajarao , KIM, Young-Hee , LINDER, Barry, P. , NARAYANAN, Vijay , PARUCHURI, Vamsi, K. , WONG, Keith, Kwong, Hon
- 申请人： International Business Machines Corporation
- 申请人地址： New Orchard Road Armonk, NY 10504 US
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： New Orchard Road Armonk, NY 10504 US
- 代理机构： Williams, Julian David
- 优先权： US111592 20050421
- 国际公布： WO2006115894 20061102
- 主分类号： H01L29/76
- IPC分类号： H01L29/76
摘要：
The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
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