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1.发明公开INTRODUCTION OF METAL IMPURITY TO CHANGE WORKFUNCTION OF CONDUCTIVE ELECTRODES 审中-公开引言金属杂质修订工作职能引出电极
公开(公告)号：EP1974372A2
公开(公告)日：2008-10-01
申请号：EP07716303.8
申请日：2007-01-03
发明人： CHUDZIK, Michael, P. , DORIS, Bruce, B. , GUHA, Supratik , JAMMY, Rajarao , NARAYANAN, Vijay , PARUCHURI, Vamsi, K. , WANG, Yun, Y. , KWONG HON WONG, Keith
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823828 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal- oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.
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2.发明公开USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES 有权金属/金属氮化物双层AS栅极电极的自对准AGGRESSIVE缩放CMOS组件使用
公开(公告)号：EP1872407A2
公开(公告)日：2008-01-02
申请号：EP06750529.7
申请日：2006-04-18
发明人： CARTIER, Eduard, A. , COPEL, Matthew, W. , DORIS, Bruce, B. , JAMMY, Rajarao , KIM, Young-Hee , LINDER, Barry, P. , NARAYANAN, Vijay , PARUCHURI, Vamsi, K. , WONG, Keith, Kwong, Hon
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
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3.发明授权USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES 有权金属/金属氮化物双层AS栅极电极的自对准AGGRESSIVE缩放CMOS组件使用
公开(公告)号：EP1872407B1
公开(公告)日：2013-09-11
申请号：EP06750529.7
申请日：2006-04-18
发明人： CARTIER, Eduard, A. , COPEL, Matthew, W. , DORIS, Bruce, B., IBM United Kingdom Ltd. , JAMMY, Rajarao, c/o IBM United Kingdom Ltd. , KIM, Young-Hee , LINDER, Barry, P. , NARAYANAN, Vijay , PARUCHURI, Vamsi, K. , WONG, Keith, Kwong, Hon
IPC分类号： H01L21/84 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842
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