发明公开
- 专利标题: 3D IC METHOD AND DEVICE
- 专利标题(中): 3D-IC-VERFAHREN UND VORRICHTUNG
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申请号: EP06789507.8申请日: 2006-08-07
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公开(公告)号: EP1913631A2公开(公告)日: 2008-04-23
- 发明人: ENQUIST, Paul, M. , FOUNTAIN, Gaius, Gillman, Jr. , TONG, Qin-Yi
- 申请人: Ziptronix, Inc.
- 申请人地址: 800 Perimeter Park Drive, Suite B Morrisville, NC 27560 US
- 专利权人: Ziptronix, Inc.
- 当前专利权人: Ziptronix, Inc.
- 当前专利权人地址: 800 Perimeter Park Drive, Suite B Morrisville, NC 27560 US
- 代理机构: Ilgart, Jean-Christophe
- 优先权: US201321 20050811
- 国际公布: WO2007021639 20070222
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure (12, 82) is bonded to a second element having a second contact structure (17, 87). First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via (50, 55) may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.; Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.
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