公开(公告)号：EP1603702A4

公开(公告)日：2008-10-29

申请号：EP04708960

申请日：2004-02-06

申请人： ZIPTRONIX INC

发明人： TONG QIN-YI ,  ENQUIST PAUL M ,  ROSE ANTHONY SCOT

IPC分类号： B23K31/00 ,  B23K20/02 ,  C04B37/00 ,  C04B37/02 ,  H01L21/60 ,  H01L21/98

CPC分类号： H01L21/76251 ,  B23K20/02 ,  H01L21/481 ,  H01L24/09 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/90 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/80801 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81014 ,  H01L2224/81136 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/83095 ,  H01L2224/8319 ,  H01L2224/8334 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83895 ,  H01L2224/83907 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/351 ,  Y10T29/49126 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

公开(公告)号：EP1913631A2

公开(公告)日：2008-04-23

申请号：EP06789507.8

申请日：2006-08-07

申请人： Ziptronix, Inc.

发明人： ENQUIST, Paul, M. ,  FOUNTAIN, Gaius, Gillman, Jr. ,  TONG, Qin-Yi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/81121 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81931 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/81

摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure (12, 82) is bonded to a second element having a second contact structure (17, 87). First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via (50, 55) may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.; Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

摘要翻译： 三维集成元件如单个模具或晶片的三维集成方法以及具有诸如单个模具或晶片的连接元件的集成结构。 芯片和晶片中的任一个或两者可以具有形成在其中的半导体器件。 具有第一接触结构（12,82）的第一元件被结合到具有第二接触结构（17,87）的第二元件。 第一和第二接触结构可以在结合时暴露，并且由于接合而电互连。 通孔（50,55）可以在结合之后进行蚀刻和填充，以暴露并形成互连的第一和第二接触结构的电互连，并提供从表面到该互连的电接口。 或者，第一接触结构和/或第二接触结构在接合时不暴露，并且通孔在接合之后进行蚀刻和填充，从而电互连第一和第二接触结构，并提供对相互连接的第一和第二接触结构与表面的电接触。 此外，器件可以形成在第一衬底中，该器件设置在第一衬底的器件区域中并且具有第一接触结构。 通孔可以在结合之前被蚀刻或蚀刻和填充穿过器件区域并进入第一衬底，并且第一衬底被稀释以露出通孔，或者在结合之后填充通孔。

公开(公告)号：EP2287896A2

公开(公告)日：2011-02-23

申请号：EP10185999.9

申请日：2001-02-15

申请人： Ziptronix, Inc.

发明人： Tong, Qin-Yi ,  Fountain, Gaius Gillman ,  Enquist, Paul M.

IPC分类号： H01L21/48

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO 2 . The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

摘要翻译： 在低或室温下接合的方法包括通过清洗或蚀刻进行表面清洁和活化的步骤。 一种蚀刻方法该方法还可以包括除去界面聚合的副产物以防止反向聚合反应，以允许诸如硅，氮化硅和SiO 2的材料的室温化学键合。 要结合的表面被抛光到高度的平滑度和平坦度。 VSE可以使用反应离子蚀刻或湿蚀刻来稍微蚀刻被结合的表面。 表面粗糙度和平面度不会降低，并且可以通过VSE工艺增强。 蚀刻的表面可以在诸如氢氧化铵或氟化铵的溶液中漂洗以促进在表面上形成所需的粘结物质。

公开(公告)号：EP1277232A4

公开(公告)日：2003-07-23

申请号：EP01920489

申请日：2001-03-22

申请人： ZIPTRONIX INC

发明人： ENQUIST PAUL M

IPC分类号： H01L31/04 ,  H01L21/02 ,  H01L21/768 ,  H01L27/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/98 ,  H01L25/065 ,  H01L27/06

CPC分类号： H01L21/76898 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/48091 ,  H01L2924/00013 ,  H01L2924/01057 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device (14) having a substrate (20) to an element (10) and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections (51) may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices (165) to an element (163), and the element may have recesses (167) in which the semiconductor devices are disposed. A conductor array (78) having a plurality of contact structures may be formed on an exposed surface of the semiconductor device (77), vias may be formed through the semiconductor device to device regions, and interconnection (81, 82, 83) may be formed between said device regions and said contact structures.

公开(公告)号：EP1277232A1

公开(公告)日：2003-01-22

申请号：EP01920489.0

申请日：2001-03-22

申请人： Ziptronix, Inc.

发明人： ENQUIST, Paul, M.

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/76898 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/48091 ,  H01L2924/00013 ,  H01L2924/01057 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device (14) having a substrate (20) to an element (10) and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections (51) may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices (165) to an element (163), and the element may have recesses (167) in which the semiconductor devices are disposed. A conductor array (78) having a plurality of contact structures may be formed on an exposed surface of the semiconductor device (77), vias may be formed through the semiconductor device to device regions, and interconnection (81, 82, 83) may be formed between said device regions and said contact structures.

摘要翻译： 一种设备集成方法和集成设备。 该方法可以包括以下步骤：将具有衬底（20）的半导体器件（14）直接接合到元件（10）;以及在接合之后去除衬底的一部分以暴露半导体器件的剩余部分。 该元件可以包括用于热扩散，阻抗匹配或RF隔离的基板，天线以及由无源元件组成的匹配网络中的一个。 第二热扩散基板可以结合到半导体器件的其余部分。 互连（51）可以通过第一或第二基板制成。 该方法还可以包括将多个半导体器件（165）结合到元件（163），并且该元件可以具有半导体器件设置在其中的凹槽（167）。 具有多个接触结构的导体阵列（78）可以形成在半导体器件（77）的暴露表面上，通孔可以形成为穿过半导体器件到器件区域，并且互连（81,82,83）可以是 形成在所述器件区域和所述接触结构之间。

公开(公告)号：EP2685491A2

公开(公告)日：2014-01-15

申请号：EP13188074.2

申请日：2006-08-07

申请人： Ziptronix, Inc.

发明人： Enquist, Paul M. ,  Fountain, Gaius, Gillman, Jr. ,  Tong, Qin-Yi

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/81121 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81931 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/81

摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure (12, 82) is bonded to a second element having a second contact structure (17, 87). First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via (50, 55) may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.; Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

摘要翻译： 三维集成元件如单个模具或晶片的三维集成方法以及具有诸如单个模具或晶片的连接元件的集成结构。 芯片和晶片中的任一个或两者可以具有形成在其中的半导体器件。 具有第一接触结构（12,82）的第一元件被结合到具有第二接触结构（17,87）的第二元件。 第一和第二接触结构可以在结合时暴露，并且由于接合而电互连。 通孔（50,55）可以在结合之后进行蚀刻和填充，以暴露并形成互连的第一和第二接触结构的电互连，并提供从表面到该互连的电接口。 或者，第一接触结构和/或第二接触结构在接合时不暴露，并且通孔在接合之后进行蚀刻和填充，从而电互连第一和第二接触结构，并提供对相互连接的第一和第二接触结构与表面的电接触。 此外，器件可以形成在第一衬底中，该器件设置在第一衬底的器件区域中并且具有第一接触结构。 通孔可以在结合之前被蚀刻或蚀刻和填充穿过器件区域并进入第一衬底，并且第一衬底被稀释以露出通孔，或者在结合之后填充通孔。

公开(公告)号：EP1678763A4

公开(公告)日：2009-12-09

申请号：EP04793947

申请日：2004-10-20

申请人： ZIPTRONIX INC

发明人： ENQUIST PAUL M

IPC分类号： H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2224/83894 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2224/83 ,  H01L2924/01015 ,  H01L2924/01031

公开(公告)号：EP1245039A2

公开(公告)日：2002-10-02

申请号：EP00968318.6

申请日：2000-09-29

申请人： Ziptronix, Inc.

发明人： ENQUIST, Paul, M.

IPC分类号： H01L21/58

CPC分类号： H01L24/08 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/13 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/26 ,  H01L24/27 ,  H01L24/30 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/3005 ,  H01L2224/30104 ,  H01L2224/305 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/8303 ,  H01L2224/83092 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/83193 ,  H01L2224/83345 ,  H01L2224/83359 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83912 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S148/012 ,  Y10S438/977 ,  H01L2224/13099 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A device integration method and integrated device. The method includes the steps of polishing surfaces of first (10) and second (30) workpieces each to a surface roughness of about 5-10Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece (32) is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1-10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies.

摘要翻译： 一种方法可以包括将具有衬底的半导体器件直接结合到元件的步骤; 以及去除所述衬底的一部分以在结合之后露出所述半导体器件的剩余部分。 元件可以包括用于热扩散，阻抗匹配或RF隔离的衬底之一，天线以及由无源元件组成的匹配网络。 第二热扩散基板可以结合到半导体器件的其余部分。 可以通过第一或第二基底进行互连。 该方法还可以包括将多个半导体器件接合到元件，并且元件可以具有设置半导体器件的凹部。

公开(公告)号：EP1913631A4

公开(公告)日：2011-10-05

申请号：EP06789507

申请日：2006-08-07

申请人： ZIPTRONIX INC

发明人： ENQUIST PAUL M ,  FOUNTAIN GAIUS GILLMAN JR ,  TONG QIN-YI

IPC分类号： H01L25/065 ,  H01L21/60 ,  H01L21/768 ,  H01L21/98 ,  H01L23/48

CPC分类号： H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/81121 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81931 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/81

摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure (12, 82) is bonded to a second element having a second contact structure (17, 87). First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via (50, 55) may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.; Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

公开(公告)号：EP1721335A4

公开(公告)日：2011-01-05

申请号：EP05713952

申请日：2005-02-23

申请人： ZIPTRONIX INC

发明人： ENQUIST PAUL M ,  FOUNTAIN GAIUS G JR ,  PETTEWAY CARL T

IPC分类号： H01L23/495 ,  A47J45/00 ,  B65G47/00 ,  H01L21/44

CPC分类号： H01L21/67333 ,  H01L2924/0002 ,  Y10S414/135 ,  Y10S414/14 ,  Y10S414/141 ,  H01L2924/00