发明公开
EP1928703A1 STEUERGERÄT MIT RECHENGERÄT UND PERIPHERIEBAUSTEIN, DIE ÜBER EINEN SERIELLEN MEHRDRAHTBUS MITEINANDER IN VERBINDUNG STEHEN 有权
与计算设备和外设BLOCK通过串行多线一起连接控制设备

  • 专利标题: STEUERGERÄT MIT RECHENGERÄT UND PERIPHERIEBAUSTEIN, DIE ÜBER EINEN SERIELLEN MEHRDRAHTBUS MITEINANDER IN VERBINDUNG STEHEN
  • 专利标题(英): Control device with a computing device and a peripheral module, which are interconnected via a serial multiwire bus
  • 专利标题(中): 与计算设备和外设BLOCK通过串行多线一起连接控制设备
  • 申请号: EP06806739.6
    申请日: 2006-09-01
  • 公开(公告)号: EP1928703A1
    公开(公告)日: 2008-06-11
  • 发明人: KNEER, AndreasAUE, Axel
  • 申请人: ROBERT BOSCH GMBH
  • 申请人地址: Postfach 30 02 20 70442 Stuttgart DE
  • 专利权人: ROBERT BOSCH GMBH
  • 当前专利权人: ROBERT BOSCH GMBH
  • 当前专利权人地址: Postfach 30 02 20 70442 Stuttgart DE
  • 优先权: DE102005042493 20050907
  • 国际公布: WO2007028771 20070315
  • 主分类号: B60R16/03
  • IPC分类号: B60R16/03 G06F13/40
STEUERGERÄT MIT RECHENGERÄT UND PERIPHERIEBAUSTEIN, DIE ÜBER EINEN SERIELLEN MEHRDRAHTBUS MITEINANDER IN VERBINDUNG STEHEN
摘要:
The invention relates to a control device (20), which comprises at least one computing device (2) and at least one separate peripheral module (21) which is connected to the computing device (2) via a serial multiwire bus (4), with at least one output stage (9) for forwarding serial data to means outside of the control device (20). In order to keep the number of pins (10) required on the peripheral module (3) to a minimum, thereby reducing the cost of the entire control device (20), it is proposed that the peripheral module (21) has an asynchronous single-wire interface (22) between an interface (8) for the serial multiwire bus (4) and the output stage (9). The asynchronous single-wire interface (22) is preferably a UART (Universal Asynchronous Receiver Transmitter) interface. The serial multiwire bus (4) is preferably a microsecond bus.
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