发明公开
- 专利标题： TRI-STATING A PHASE LOCKED LOOP TO CONSERVE POWER
- 专利标题（中）： A相三态锁定环能节电
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申请号： EP06814633.1申请日： 2006-09-12
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公开(公告)号： EP1929632A2公开(公告)日： 2008-06-11
- 发明人: GEHRING, Mark, R. , MOYAL, Nathan
- 申请人： CYPRESS SEMICONDUCTOR CORPORATION
- 申请人地址： 198 Champion Court San Jose, CA 95134-1709 US
- 专利权人： CYPRESS SEMICONDUCTOR CORPORATION
- 当前专利权人： CYPRESS SEMICONDUCTOR CORPORATION
- 当前专利权人地址： 198 Champion Court San Jose, CA 95134-1709 US
- 代理机构： Betten & Resch
- 优先权： US720858P 20050926; US467346 20060825
- 国际公布： WO2007037991 20070405
- 主分类号： H03L7/00
- IPC分类号： H03L7/00
摘要：
In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.
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