利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

106 条记录 (耗时 0.016 秒)

    SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER
    2.
    发明公开
    SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER 审中-公开

    公开(公告)号：EP3534408A1

    公开(公告)日：2019-09-04

    申请号：EP18213110.2

    申请日：2013-03-08

    申请人： Cypress Semiconductor Corporation

    发明人： JENNE, Fredrick ,  RAMKUMAR, Krishnaswamy

    IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/51 ,  H01L27/11582 ,  H01L29/06 ,  H01L29/78

    摘要： Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.

    SIGNAL PROCESSOR UNIT AND COMMUNICATION DEVICE
    3.
    发明授权
    SIGNAL PROCESSOR UNIT AND COMMUNICATION DEVICE 有权
    信号处理器单元和通信设备

    公开(公告)号：EP2207308B1

    公开(公告)日：2018-03-14

    申请号：EP07831164.4

    申请日：2007-11-02

    申请人： Cypress Semiconductor Corporation

    发明人： SHIMAMURA, Akira ,  FUJISHIMA, Hideshi ,  MITA, Koichi ,  ARAI, Takashi ,  ENDO, Akira

    IPC分类号： H04J3/06 ,  H04L12/28 ,  H04L12/40

    CPC分类号： H04J3/06 ,  H04L12/40006 ,  H04L12/40032 ,  H04L69/14 ,  H04L2012/40241

    摘要： A signal processor related to frame communication which is proceeded based on allocated unit communication periods, in which each communication device recognizes the end of communication of a frame based on a received signal, and then starts a communication action of the next frame, the signal processor has a period detection section which detects that a period is currently used for communication of a frame; a pattern detection section which detects, from the received signal, a first signal pattern by which the end of communication of the frame is recognized; and an output processing section which outputs the received signal to a controller connected thereto, configured to instruct, upon detection of the first signal pattern in the period being currently used for communication of a frame, the controller to halt startup of communication action of the next frame, until the period being currently used for communication of a frame comes to the end, to thereby prevent an event such that frames are transmitted from a plurality of communication devices simultaneously, and to thereby allow the communication action for the next frame to proceed correctly.

    METHOD FOR PROVIDING PACKET FRAMING IN A DSSS RADIO SYSTEM
    7.
    发明公开
    METHOD FOR PROVIDING PACKET FRAMING IN A DSSS RADIO SYSTEM 审中-公开
    方法分组取景IN A DSSS无线电系统交付

    公开(公告)号：EP1792413A2

    公开(公告)日：2007-06-06

    申请号：EP05794319.3

    申请日：2005-08-31

    申请人： CYPRESS SEMICONDUCTOR CORPORATION

    发明人： WRIGHT, David

    IPC分类号： H04B1/707

    CPC分类号： H04J13/0022 ,  H04J13/16

    摘要： An improved method of framing data packets in a direct sequence spread spectrum (DSSS) system that uses one pseudo-noise code (PN-Code) to frame the packet with a start-of-packet (SOP) and end-of-packet (EOP) indicator, and a different PN­Code to encode the data payload. Furthermore, the SOP is represented by the framing PN-Code, and the EOP is represented by the inverse of the framing PN­Code. This method creates a robust framing system that enables a DSSS system to operate with a low threshold of detection, thus maximizing transmission range even in noisy environments. Additionally, the PN-Code used for the SOP and EOP indicators can be used to indicate an acknowledgement response.

    Method and circuit for reading a potentiometer
    8.
    发明公开
    Method and circuit for reading a potentiometer 审中-公开
    的方法和电路，用于读取一个电位

    公开(公告)号：EP1404021A3

    公开(公告)日：2006-06-28

    申请号：EP03255412.3

    申请日：2003-08-29

    申请人： CYPRESS SEMICONDUCTOR CORPORATION

    发明人： Hatton, Barry S. ,  Wright, David G.

    IPC分类号： H03M1/50 ,  G01R27/02

    CPC分类号： H03M1/50

    摘要： Embodiments of the invention describe a method and apparatus used to determine the position of a wiper on a potentiometer without the need for an external ADC. Two capacitors are each connected to an end of a potentiometer, and then are charged or discharged simultaneously by a current source or current sink attached to the wiper of the potentiometer. The time required for each of the capacitors to charge or discharge to a threshold voltage level is measured and subsequently used to determine the position of the wiper on the potentiometer.

    Method and circuit for reading a potentiometer
    10.
    发明公开
    Method and circuit for reading a potentiometer 审中-公开
    Verfahren und Schaltung zum Lesen eines电位器

    公开(公告)号：EP1404021A2

    公开(公告)日：2004-03-31

    申请号：EP03255412.3

    申请日：2003-08-29

    申请人： CYPRESS SEMICONDUCTOR CORPORATION

    发明人： Hatton, Barry S. ,  Wright, David G.

    IPC分类号： H03M1/50

    CPC分类号： H03M1/50

    摘要： Embodiments of the invention describe a method and apparatus used to determine the position of a wiper on a potentiometer without the need for an external ADC. Two capacitors are each connected to an end of a potentiometer, and then are charged or discharged simultaneously by a current source or current sink attached to the wiper of the potentiometer. The time required for each of the capacitors to charge or discharge to a threshold voltage level is measured and subsequently used to determine the position of the wiper on the potentiometer.

    摘要翻译： 该方法涉及当耦合到电位计（40）的端部（42）的电容器（62）的电压达到参考电压时记录定时器读数。 当耦合到电位器的另一端（46）的电容器（66）的电压达到参考电压时，记录另一定时读数。 然后将两个记录的定时器读数进行比较，以确定擦拭器（41）的相对位置。 还包括用于读取电位器的设备的独立权利要求。