发明授权
EP1984814B1 METHOD AND APPARATUS FOR ENFORCING MEMORY REFERENCE ORDERING REQUIREMENTS AT THE L1 CACHE LEVEL
有权
用于在L1高速缓存级别上执行存储器参考订购要求的方法和设备
- 专利标题: METHOD AND APPARATUS FOR ENFORCING MEMORY REFERENCE ORDERING REQUIREMENTS AT THE L1 CACHE LEVEL
- 专利标题(中): 用于在L1高速缓存级别上执行存储器参考订购要求的方法和设备
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申请号: EP07717171.8申请日: 2007-02-02
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公开(公告)号: EP1984814B1公开(公告)日: 2018-03-28
- 发明人: CHAUDHRY, Shailender , TREMBLAY, Marc
- 申请人: Oracle America, Inc.
- 申请人地址: 500 Oracle Parkway Redwood City, CA 94065 US
- 专利权人: Oracle America, Inc.
- 当前专利权人: Oracle America, Inc.
- 当前专利权人地址: 500 Oracle Parkway Redwood City, CA 94065 US
- 代理机构: D Young & Co LLP
- 优先权: US765945P 20060206; US592836 20061103
- 国际公布: WO2007092273 20070816
- 主分类号: G06F9/38
- IPC分类号: G06F9/38
摘要:
One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution mode, the system receives an invalidation signal for a cache line at the L1 cache wherein the invalidation signal is received from a cache-coherence system within the multiprocessor. In response to the invalidation signal, if the cache line exists in the L1 cache, the system examines a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during speculative execution. If the load-mark is set, the system fails the speculative-execution mode and resumes a normal-execution mode from a checkpoint. By failing the speculative-execution mode, the system ensures that a potential update to the cache line indicated by the invalidation signal will not cause the memory reference ordering requirements to be violated during the speculative-execution mode.
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