公开(公告)号：EP1984814B1

公开(公告)日：2018-03-28

申请号：EP07717171.8

申请日：2007-02-02

申请人： Oracle America, Inc.

发明人： CHAUDHRY, Shailender ,  TREMBLAY, Marc

IPC分类号： G06F9/38

CPC分类号： G06F9/3834 ,  G06F9/30189 ,  G06F9/3842 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution mode, the system receives an invalidation signal for a cache line at the L1 cache wherein the invalidation signal is received from a cache-coherence system within the multiprocessor. In response to the invalidation signal, if the cache line exists in the L1 cache, the system examines a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during speculative execution. If the load-mark is set, the system fails the speculative-execution mode and resumes a normal-execution mode from a checkpoint. By failing the speculative-execution mode, the system ensures that a potential update to the cache line indicated by the invalidation signal will not cause the memory reference ordering requirements to be violated during the speculative-execution mode.

公开(公告)号：EP1994471B1

公开(公告)日：2017-12-13

申请号：EP07762866.7

申请日：2007-02-01

申请人： Oracle America, Inc.

发明人： CAPRIOLI, Paul ,  CHAUDHRY, Shailender

IPC分类号： G06F12/10 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/30054 ,  G06F12/0875 ,  G06F12/10 ,  G06F2212/655 ,  Y02D10/13

摘要： Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation reduces power consumption and increases pipeline efficiency since accessing of an address translation buffer can be avoided. Certain events, such as branch mis-predictions and exceptions, can be designated as page boundary crossing events. In addition, carry over at a particular bit position when computing a branch target or a next instruction instance fetch target can also be designated as a page boundary crossing event. An address translation buffer is accessed to translate an address representation of a first instruction instance. However, until a page boundary crossing event occurs, the address representations of subsequent instruction instances are not translated. Instead, the translated portion of the address representation for the first instruction instance is recycled for the subsequent instruction instances.

公开(公告)号：EP2074511B1

公开(公告)日：2017-05-24

申请号：EP07842387.8

申请日：2007-09-13

申请人： Oracle America, Inc.

发明人： CYPHER, Robert E. ,  CHAUDHRY, Shailender

IPC分类号： G06F9/38

CPC分类号： G06F9/3834 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3867 ,  G06F12/0897

公开(公告)号：EP1673692B1

公开(公告)日：2013-03-13

申请号：EP04784741.3

申请日：2004-09-09

申请人： Oracle America, Inc.

发明人： CHAUDHRY, Shailender ,  TREMBLAY, Marc

IPC分类号： G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865

公开(公告)号：EP1316015B1

公开(公告)日：2010-12-29

申请号：EP01966737.7

申请日：2001-08-30

申请人： Oracle America, Inc.

发明人： CHAUDHRY, Shailender ,  TREMBLAY, Marc

IPC分类号： G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/3808 ,  G06F9/3879

摘要： One embodiment of the present invention provides a system that prefetches instructions by using an assist processor to perform prefetch operations in advance of a primary processor. The system operates by executing executable code on the primary processor, and simultaneously executing a reduced version of the executable code on the assist processor. This reduced version of the executable code executes more quickly than the executable code, and performs prefetch operations for the primary processor in advance of when the primary processor requires the instructions. The system also stores the prefetched instructions into a cache that is accessible by the primary processor so that the primary processor is able to access the prefetched instructions without having to retrieve the prefetched instructions from a main memory. In one embodiment of the present invention, prior to executing the executable code, the system compiles source code into executable code for the primary processor. Next, the system profiles the executable code to create instruction traces for frequently referenced portions of the executable code. The system then produces the reduced version of the executable code for the assist processor by producing prefetch instructions to prefetch portions of the instruction traces into a cache that is accessible by the primary processor. The system also inserts communication instructions into the executable code for the primary processor and into the reduced version of the executable code for the assist processor to transfer progress information from the primary processor to the assist processor. This progress information triggers the assist processor to perform the prefetch operations.

公开(公告)号：EP1999575B1

公开(公告)日：2017-11-22

申请号：EP07717177.5

申请日：2007-02-02

申请人： Oracle America, Inc.

发明人： CHAUDHRY, Shailender ,  TREMBLAY, Marc ,  CAPRIOLI, Paul

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3863

公开(公告)号：EP2422270A2

公开(公告)日：2012-02-29

申请号：EP10721863.8

申请日：2010-04-13

申请人： Oracle America, Inc. formerly known as Sun Microsystems, Inc.

发明人： CHAUDHRY, Shailender ,  TREMBLAY, Marc

IPC分类号： G06F9/30

CPC分类号： G06F9/30098 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3838 ,  G06F9/384

摘要： A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.

公开(公告)号：EP1399823B1

公开(公告)日：2011-02-16

申请号：EP02752292.9

申请日：2002-06-26

申请人： Oracle America, Inc.

发明人： CHAUDHRY, Shailender ,  TREMBLAY, Marc

IPC分类号： G06F12/08

CPC分类号： G06F9/3842 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0828

摘要： One embodiment of the present invention provides a system that facilitates speculative load operations in a multiprocessor system. This system operates by maintaining a record at an L2 cache of speculative load operations that have returned data values through the L2 cache to associated L1 caches, wherein a speculative load operation is a load operation that is speculatively initiated before a preceding load operation has returned. In response to receiving an invalidation event, the system invalidates a target line in the L2 cache. The system also performs a lookup in the record to identify affected L1 caches that are associated with speculative load operations that may be affected by the invalidation of the target line in the L2 cache. Next, the system sends replay commands to the affected L1 caches in order to replay the affected speculative load operations, so that the affected speculative load operations take place after invalidation of the target line in the L2 cache.