发明公开
- 专利标题： LOGIC DEVICE AND METHOD SUPPORTING SCAN TEST
- 专利标题（中）： LOGIC的系统和方法用于支持扫描测试
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申请号： EP07784466.0申请日： 2007-06-18
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公开(公告)号： EP2030032A2公开(公告)日： 2009-03-04
- 发明人: SAINT-LAURENT, Martin , BASSETT, Paul , PATEL, Prayag
- 申请人： QUALCOMM Incorporated
- 申请人地址： Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121 US
- 专利权人： QUALCOMM Incorporated
- 当前专利权人： QUALCOMM Incorporated
- 当前专利权人地址： Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121 US
- 代理机构： Dunlop, Hugh Christopher
- 优先权： US473219 20060622
- 国际公布： WO2007149808 20071227
- 主分类号： G01R31/3185
- IPC分类号： G01R31/3185
摘要：
A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.
公开/授权文献
- EP2030032B1 LOGIC DEVICE AND METHOD SUPPORTING SCAN TEST 公开/授权日：2012-05-23
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