公开(公告)号：EP2030032A2

公开(公告)日：2009-03-04

申请号：EP07784466.0

申请日：2007-06-18

申请人： QUALCOMM Incorporated

发明人： SAINT-LAURENT, Martin ,  BASSETT, Paul ,  PATEL, Prayag

IPC分类号： G01R31/3185

CPC分类号： G01R31/318552 ,  G01R31/3025 ,  G01R31/318575

摘要： A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.

公开(公告)号：EP2030032B1

公开(公告)日：2012-05-23

申请号：EP07784466.0

申请日：2007-06-18

申请人： QUALCOMM Incorporated

发明人： SAINT-LAURENT, Martin ,  BASSETT, Paul ,  PATEL, Prayag

IPC分类号： G01R31/3185

CPC分类号： G01R31/318552 ,  G01R31/3025 ,  G01R31/318575

摘要： A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.